stm32f1: Initial support for serial over USB
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
1302514ea8
commit
bc5e961d73
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@ -20,10 +20,14 @@ STM32F1 port.
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Fixed pins
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==========
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The UART used for communication with the host is fixed to pins PA9 (TX) and PA10
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(RX). SWD pins (PA13/PA14) are enabled for debugging and cannot be used for any
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I/O. SPI uses pins PB13/PB14/PB15, but the pins can be used as general I/O if
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SPI is not used.
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When using serial, the UART used for communication with the host is
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fixed to pins PA9 (TX) and PA10 (RX). When using USB, the PA11 (D-)
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and PA12 (D+) pins are reserved. The USB code assumes that PA12 (D+)
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has a fixed pullup resistor attached to it.
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SWD pins (PA13/PA14) are enabled for debugging and cannot be used for
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any I/O. SPI uses pins PB13/PB14/PB15, but the pins can be used as
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general I/O if SPI is not used.
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Digital I/O
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===========
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@ -18,10 +18,13 @@ config CLOCK_FREQ
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int
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default 8000000 # 72000000 / 9
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config USBSERIAL
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bool "Use USB for communication (instead of serial)"
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default y
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config SERIAL
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depends on !USBSERIAL
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bool
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default y
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config SERIAL_BAUD
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depends on SERIAL
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int "Baud rate for serial port"
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@ -28,6 +28,7 @@ src-y += $(addprefix ../, $(wildcard lib/hal-stm32f1/source/stm32f1xx_ll_*.c))
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src-y += generic/crc16_ccitt.c generic/armcm_irq.c generic/timer_irq.c
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src-y += ../lib/cmsis-stm32f1/source/system_stm32f1xx.c
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src-ys = ../lib/cmsis-stm32f1/source/startup_stm32f103xb.s
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src-$(CONFIG_USBSERIAL) += stm32f1/usbserial.c generic/usb_cdc.c
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src-$(CONFIG_SERIAL) += stm32f1/serial.c generic/serial_irq.c
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# Build the additional hex output file
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@ -0,0 +1,281 @@
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// Hardware interface to "fullspeed USB controller" on stm32f1
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//
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// Copyright (C) 2018 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // NULL
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#include "board/io.h" // writeb
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#include "board/usb_cdc.h" // usb_notify_ep0
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#include "board/usb_cdc_ep.h" // USB_CDC_EP_BULK_IN
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#include "sched.h" // DECL_INIT
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#include "stm32f1xx.h" // USB
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/****************************************************************
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* USB transfer memory
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****************************************************************/
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struct ep_desc {
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uint32_t addr_tx, count_tx, addr_rx, count_rx;
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};
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struct ep_mem {
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struct ep_desc ep0, ep_acm, ep_bulk_out, ep_bulk_in;
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uint32_t ep0_tx[USB_CDC_EP0_SIZE / 2];
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uint32_t ep0_rx[USB_CDC_EP0_SIZE / 2];
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uint32_t ep_acm_tx[USB_CDC_EP_ACM_SIZE / 2];
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uint32_t ep_bulk_out_rx[USB_CDC_EP_BULK_OUT_SIZE / 2];
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uint32_t ep_bulk_in_tx[USB_CDC_EP_BULK_IN_SIZE / 2];
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};
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#define USB_BTABLE ((struct ep_mem *)(USB_BASE + 0x400))
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#define CALC_ADDR(p) (((void*)(p) - (void*)USB_BTABLE) / 2)
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#define CALC_SIZE(s) ((s) > 32 ? (DIV_ROUND_UP((s), 32) << 10) | 0x8000 \
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: DIV_ROUND_UP((s), 2) << 10)
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// Setup the transfer descriptors in dedicated usb memory
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static void
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btable_configure(void)
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{
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USB_BTABLE->ep0.count_tx = 0;
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USB_BTABLE->ep0.addr_tx = CALC_ADDR(USB_BTABLE->ep0_tx);
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USB_BTABLE->ep0.count_rx = CALC_SIZE(USB_CDC_EP0_SIZE);
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USB_BTABLE->ep0.addr_rx = CALC_ADDR(USB_BTABLE->ep0_rx);
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USB_BTABLE->ep_acm.count_tx = 0;
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USB_BTABLE->ep_acm.addr_tx = CALC_ADDR(USB_BTABLE->ep_acm_tx);
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USB_BTABLE->ep_bulk_out.count_rx = CALC_SIZE(USB_CDC_EP_BULK_OUT_SIZE);
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USB_BTABLE->ep_bulk_out.addr_rx = CALC_ADDR(USB_BTABLE->ep_bulk_out_rx);
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USB_BTABLE->ep_bulk_in.count_tx = 0;
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USB_BTABLE->ep_bulk_in.addr_tx = CALC_ADDR(USB_BTABLE->ep_bulk_in_tx);
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}
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// Read a packet stored in dedicated usb memory
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static void
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btable_read_packet(uint8_t *dest, uint32_t *src, int count)
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{
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uint_fast8_t i;
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for (i=0; i<(count/2); i++) {
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uint32_t d = *src++;
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*dest++ = d;
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*dest++ = d >> 8;
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}
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if (count & 1)
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*dest = *src;
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}
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// Write a packet to dedicated usb memory
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static void
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btable_write_packet(uint32_t *dest, const uint8_t *src, int count)
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{
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int i;
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for (i=0; i<(count/2); i++) {
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uint8_t b1 = *src++, b2 = *src++;
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*dest++ = b1 | (b2 << 8);
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}
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if (count & 1)
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*dest = *src;
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}
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/****************************************************************
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* USB endpoint register
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****************************************************************/
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#define USB_EPR ((volatile uint32_t *)USB_BASE)
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#define EP_BULK (0 << USB_EP0R_EP_TYPE_Pos)
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#define EP_CONTROL (1 << USB_EP0R_EP_TYPE_Pos)
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#define EP_INTERRUPT (3 << USB_EP0R_EP_TYPE_Pos)
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#define RX_STALL (1 << USB_EP0R_STAT_RX_Pos)
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#define RX_NAK (2 << USB_EP0R_STAT_RX_Pos)
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#define RX_VALID (3 << USB_EP0R_STAT_RX_Pos)
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#define TX_STALL (1 << USB_EP0R_STAT_TX_Pos)
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#define TX_NAK (2 << USB_EP0R_STAT_TX_Pos)
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#define TX_VALID (3 << USB_EP0R_STAT_TX_Pos)
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#define EPR_RWBITS (USB_EP0R_EA | USB_EP0R_EP_KIND | USB_EP0R_EP_TYPE)
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#define EPR_RWCBITS (USB_EP0R_CTR_RX | USB_EP0R_CTR_TX)
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static uint32_t
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set_stat_rx_bits(uint32_t epr, uint32_t bits)
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{
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return ((epr & (EPR_RWBITS | USB_EP0R_STAT_RX_Msk)) ^ bits) | EPR_RWCBITS;
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}
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static uint32_t
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set_stat_tx_bits(uint32_t epr, uint32_t bits)
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{
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return ((epr & (EPR_RWBITS | USB_EP0R_STAT_TX_Msk)) ^ bits) | EPR_RWCBITS;
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}
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static uint32_t
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set_stat_rxtx_bits(uint32_t epr, uint32_t bits)
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{
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uint32_t mask = EPR_RWBITS | USB_EP0R_STAT_RX_Msk | USB_EP0R_STAT_TX_Msk;
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return ((epr & mask) ^ bits) | EPR_RWCBITS;
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}
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/****************************************************************
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* USB interface
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****************************************************************/
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int_fast8_t
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usb_read_bulk_out(void *data, uint_fast8_t max_len)
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{
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uint32_t epr = USB_EPR[USB_CDC_EP_BULK_OUT];
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if ((epr & USB_EP0R_STAT_RX_Msk) == RX_VALID)
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// No data ready
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return -1;
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uint32_t count = USB_BTABLE->ep_bulk_out.count_rx & 0x3ff;
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if (count > max_len)
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count = max_len;
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btable_read_packet(data, USB_BTABLE->ep_bulk_out_rx, count);
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USB_EPR[USB_CDC_EP_BULK_OUT] = set_stat_rx_bits(epr, RX_VALID);
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return count;
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}
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int_fast8_t
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usb_send_bulk_in(void *data, uint_fast8_t len)
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{
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uint32_t epr = USB_EPR[USB_CDC_EP_BULK_IN];
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if ((epr & USB_EP0R_STAT_TX_Msk) != TX_NAK)
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// No buffer space available
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return -1;
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btable_write_packet(USB_BTABLE->ep_bulk_in_tx, data, len);
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USB_BTABLE->ep_bulk_in.count_tx = len;
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USB_EPR[USB_CDC_EP_BULK_IN] = set_stat_tx_bits(epr, TX_VALID);
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return len;
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}
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int_fast8_t
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usb_read_ep0(void *data, uint_fast8_t max_len)
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{
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uint32_t epr = USB_EPR[0];
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if ((epr & USB_EP0R_STAT_RX_Msk) != RX_NAK)
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// No data ready
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return -1;
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uint32_t count = USB_BTABLE->ep0.count_rx & 0x3ff;
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if (count > max_len)
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count = max_len;
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btable_read_packet(data, USB_BTABLE->ep0_rx, count);
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USB_EPR[0] = set_stat_rxtx_bits(epr, RX_VALID | TX_NAK);
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return count;
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}
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int_fast8_t
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usb_read_ep0_setup(void *data, uint_fast8_t max_len)
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{
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return usb_read_ep0(data, max_len);
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}
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int_fast8_t
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usb_send_ep0(const void *data, uint_fast8_t len)
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{
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uint32_t epr = USB_EPR[0];
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if ((epr & USB_EP0R_STAT_RX_Msk) != RX_VALID)
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// Transfer interrupted
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return -2;
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if ((epr & USB_EP0R_STAT_TX_Msk) != TX_NAK)
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// No buffer space available
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return -1;
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btable_write_packet(USB_BTABLE->ep0_tx, data, len);
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USB_BTABLE->ep0.count_tx = len;
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USB_EPR[0] = set_stat_tx_bits(epr, TX_VALID);
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return len;
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}
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void
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usb_stall_ep0(void)
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{
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USB_EPR[0] = set_stat_rxtx_bits(USB_EPR[0], RX_STALL | TX_STALL);
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}
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static uint8_t set_address;
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void
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usb_set_address(uint_fast8_t addr)
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{
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writeb(&set_address, addr | USB_DADDR_EF);
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usb_send_ep0(NULL, 0);
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}
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void
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usb_set_configure(void)
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{
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}
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/****************************************************************
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* Setup and interrupts
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****************************************************************/
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// Initialize the usb controller
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void
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usb_init(void)
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{
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// Setup USB packet memory
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btable_configure();
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// Enable USB clock
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RCC->APB1ENR |= RCC_APB1ENR_USBEN;
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// Reset usb controller and enable interrupts
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USB->CNTR = USB_CNTR_FRES;
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USB->BTABLE = 0;
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USB->DADDR = 0;
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USB->CNTR = USB_CNTR_RESETM;
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USB->ISTR = 0;
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NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 1);
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NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
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}
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DECL_INIT(usb_init);
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// Configure interface after a USB reset event
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static void
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usb_reset(void)
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{
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USB_EPR[0] = 0 | EP_CONTROL | RX_VALID | TX_NAK;
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USB_EPR[USB_CDC_EP_ACM] = USB_CDC_EP_ACM | EP_INTERRUPT | RX_NAK | TX_NAK;
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USB_EPR[USB_CDC_EP_BULK_OUT] = (USB_CDC_EP_BULK_OUT | EP_BULK
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| RX_VALID | TX_NAK);
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USB_EPR[USB_CDC_EP_BULK_IN] = (USB_CDC_EP_BULK_IN | EP_BULK
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| RX_NAK | TX_NAK);
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USB->CNTR = USB_CNTR_CTRM | USB_CNTR_RESETM;
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USB->DADDR = USB_DADDR_EF;
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}
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// Main irq handler
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void __visible
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USB_LP_CAN1_RX0_IRQHandler(void)
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{
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uint32_t istr = USB->ISTR;
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if (istr & USB_ISTR_CTR) {
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// Endpoint activity
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uint32_t ep = istr & USB_ISTR_EP_ID;
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uint32_t epr = USB_EPR[ep];
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USB_EPR[ep] = epr & EPR_RWBITS;
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if (ep == 0) {
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usb_notify_ep0();
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if (epr & USB_EP_CTR_TX && set_address) {
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// Apply address after last "in" message transmitted
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USB->DADDR = set_address;
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set_address = 0;
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}
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} else if (ep == USB_CDC_EP_BULK_OUT) {
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usb_notify_bulk_out();
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} else if (ep == USB_CDC_EP_BULK_IN) {
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usb_notify_bulk_in();
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}
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}
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if (istr & USB_ISTR_RESET) {
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// USB Reset
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USB->ISTR = (uint16_t)~USB_ISTR_RESET;
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usb_reset();
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}
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}
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