rp2040: add chipid support
The rp2040 doesn't have a chip ID, but the flash chip connected does. We can get this ID by asking the flash chip directly, but doing so requires disengaging the XIP layer, performing the interrogation of the flash chip, and then re-enabling the XIP layer. This gives us a 64-bit unique ID that we can use as our USB serial number. Signed-off-by: Lasse Dalegaard <dalegaard@gmail.com>
This commit is contained in:
parent
0597210cb9
commit
ba958468b7
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@ -9,6 +9,7 @@ config RP2040_SELECT
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select HAVE_GPIO_ADC
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select HAVE_GPIO_ADC
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select HAVE_GPIO_BITBANGING
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select HAVE_GPIO_BITBANGING
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select HAVE_STRICT_TIMING
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select HAVE_STRICT_TIMING
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select HAVE_CHIPID
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config BOARD_DIRECTORY
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config BOARD_DIRECTORY
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string
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string
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@ -17,6 +17,7 @@ src-y += rp2040/main.c rp2040/gpio.c rp2040/adc.c generic/crc16_ccitt.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-y += generic/timer_irq.c rp2040/timer.c rp2040/bootrom.c
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src-y += generic/timer_irq.c rp2040/timer.c rp2040/bootrom.c
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src-$(CONFIG_USBSERIAL) += rp2040/usbserial.c generic/usb_cdc.c
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src-$(CONFIG_USBSERIAL) += rp2040/usbserial.c generic/usb_cdc.c
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src-$(CONFIG_USBSERIAL) += rp2040/chipid.c
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src-$(CONFIG_SERIAL) += rp2040/serial.c generic/serial_irq.c
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src-$(CONFIG_SERIAL) += rp2040/serial.c generic/serial_irq.c
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# rp2040 stage2 building
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# rp2040 stage2 building
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@ -5,8 +5,17 @@
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// This file may be distributed under the terms of the GNU GPLv3 license.
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <stdint.h> // uint16_t, uint32_t, uintptr_t
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#include <stdint.h> // uint16_t, uint32_t, uintptr_t
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#include <string.h> // memcpy
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#include "compiler.h" // noinline, __section
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static void *
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#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
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// All functions in here need to be RAM-resident, as we may need
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// to (especially for the flash functions) call while the XIP layer
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// is unavailable.
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#define noinline_ram noinline __section(".ramfunc.read_chip_id")
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static void * noinline_ram
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rom_func_lookup(uint32_t code)
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rom_func_lookup(uint32_t code)
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{
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{
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// Table and lookup function are provided by the BOOTROM
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// Table and lookup function are provided by the BOOTROM
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@ -16,10 +25,31 @@ rom_func_lookup(uint32_t code)
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return fn(table, code);
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return fn(table, code);
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}
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}
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void
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void noinline_ram
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reset_to_usb_boot(uint32_t gpio_activity_pin_mask
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reset_to_usb_boot(uint32_t gpio_activity_pin_mask
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, uint32_t disable_interface_mask)
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, uint32_t disable_interface_mask)
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{
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{
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void (*reset_to_usb_boot)(uint32_t, uint32_t) = rom_func_lookup(0x4255);
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void (*fn)(uint32_t, uint32_t) = rom_func_lookup(ROM_TABLE_CODE('U', 'B'));
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reset_to_usb_boot(gpio_activity_pin_mask, disable_interface_mask);
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fn(gpio_activity_pin_mask, disable_interface_mask);
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}
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void noinline_ram
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connect_internal_flash(void)
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{
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void (*fn)(void) = rom_func_lookup(ROM_TABLE_CODE('I', 'F'));
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fn();
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}
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void noinline_ram
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flash_exit_xip(void)
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{
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void (*fn)(void) = rom_func_lookup(ROM_TABLE_CODE('E', 'X'));
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fn();
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}
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void noinline_ram
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flash_flush_cache(void)
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{
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void (*fn)(void) = rom_func_lookup(ROM_TABLE_CODE('F', 'C'));
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fn();
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}
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}
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@ -0,0 +1,132 @@
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// Support for extracting the hardware chip id on rp2040
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//
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// Copyright (C) 2021 Lasse Dalegaard <dalegaard@gmail.com>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#define CHIP_UID_LEN 8
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#include <string.h> // memcpy
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#include "autoconf.h" // CONFIG_USB_SERIAL_NUMBER_CHIPID
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#include "board/irq.h" // irq_disable, irq_enable
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#include "generic/usb_cdc.h" // usb_fill_serial
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#include "generic/usbstd.h" // usb_string_descriptor
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#include "sched.h" // DECL_INIT
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#include "hardware/structs/ioqspi.h" // ioqspi_hw
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#include "hardware/structs/ssi.h" // ssi_hw
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#include "internal.h"
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static struct {
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struct usb_string_descriptor desc;
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uint16_t data[CHIP_UID_LEN * 2];
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} cdc_chipid;
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struct usb_string_descriptor *
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usbserial_get_serialid(void)
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{
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return &cdc_chipid.desc;
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}
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// Functions for reading out the flash chip ID. Adapted from the official
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// Pi SDK.
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static void noinline __section(".ramfunc.read_chip_id")
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flash_cs_force(int high)
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{
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uint32_t field_val = high ?
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IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH :
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IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW;
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hw_write_masked(&ioqspi_hw->io[1].ctrl,
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field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB,
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IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS
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);
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}
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// To re-enable XIP we need to call flash_enter_xip. It's available in the
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// bootrom, but that version is a generic one that works for most devices and
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// the tradeoff for that is enabling a low performance mode.
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// Instead we copy out the boot2 XIP enabling stage, and save it in RAM
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// so we can call it later on.
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#define BOOT2_SIZE 0x100
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static uint8_t boot2_copy[BOOT2_SIZE] __aligned(16);
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static void
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flash_enter_xip_prepare(void)
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{
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void * volatile target = (void *)XIP_BASE; // Avoids warning
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memcpy(boot2_copy, target, BOOT2_SIZE);
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barrier();
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}
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static void noinline __section(".ramfunc.read_chip_id")
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flash_enter_xip_perform(void)
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{
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((void (*)(void))boot2_copy+1)();
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}
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#define FLASH_RUID_CMD 0x4B
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#define FLASH_RUID_DUMMY_BYTES 4
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#define FLASH_RUID_DATA_BYTES 8
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#define FLASH_RUID_TOTAL_BYTES (1+FLASH_RUID_DUMMY_BYTES+FLASH_RUID_DATA_BYTES)
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static void noinline __section(".ramfunc.read_chip_id")
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read_unique_id(uint8_t *out)
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{
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uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0};
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uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0};
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uint8_t *txptr = txbuf;
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uint8_t *rxptr = rxbuf;
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int tx_remaining = FLASH_RUID_TOTAL_BYTES;
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int rx_remaining = FLASH_RUID_TOTAL_BYTES;
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txbuf[0] = FLASH_RUID_CMD;
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// Set up flash so we can work with it without XIP getting in the way
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flash_enter_xip_prepare();
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irq_disable();
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barrier();
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connect_internal_flash();
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flash_exit_xip();
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flash_cs_force(0);
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while (tx_remaining || rx_remaining) {
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uint32_t flags = ssi_hw->sr;
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int can_put = !!(flags & SSI_SR_TFNF_BITS);
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int can_get = !!(flags & SSI_SR_RFNE_BITS);
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if (can_put && tx_remaining) {
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ssi_hw->dr0 = *txptr++;
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tx_remaining--;
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}
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if (can_get && rx_remaining) {
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*rxptr++ = (uint8_t)ssi_hw->dr0;
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--rx_remaining;
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}
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}
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// Restore XIP
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flash_cs_force(1);
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flash_flush_cache();
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flash_enter_xip_perform();
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barrier();
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irq_enable();
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memcpy(out, rxbuf+1+FLASH_RUID_DUMMY_BYTES, FLASH_RUID_DATA_BYTES);
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}
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void
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chipid_init(void)
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{
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if (!CONFIG_USB_SERIAL_NUMBER_CHIPID)
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return;
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uint8_t data[8] = {0};
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read_unique_id(data);
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usb_fill_serial(&cdc_chipid.desc, ARRAY_SIZE(cdc_chipid.data)
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, data);
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}
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DECL_INIT(chipid_init);
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@ -10,5 +10,8 @@ uint32_t get_pclock_frequency(uint32_t reset_bit);
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void gpio_peripheral(uint32_t gpio, int func, int pull_up);
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void gpio_peripheral(uint32_t gpio, int func, int pull_up);
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void reset_to_usb_boot(uint32_t gpio_activity_pin_mask
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void reset_to_usb_boot(uint32_t gpio_activity_pin_mask
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, uint32_t disable_interface_mask);
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, uint32_t disable_interface_mask);
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void connect_internal_flash(void);
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void flash_exit_xip(void);
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void flash_flush_cache(void);
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#endif // internal.h
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#endif // internal.h
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