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stm32: add STM32H723 support 

Signed-off-by: Chen.BJ from BigTreeTech chenbj@biqu3d.com
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
bigtreetech 2022-11-23 11:29:44 +08:00 committed by Kevin O'Connor
parent 50b2e2e67e
commit a42f615881
5 changed files with 119 additions and 61 deletions
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6
klippy/extras/temperature_mcu.py
View File

@ -74,6 +74,7 @@ class PrinterTemperatureMCU:
('stm32g0', self.config_stm32g0),
('stm32g4', self.config_stm32g0),
('stm32l4', self.config_stm32g0),
('stm32h723', self.config_stm32h723),
('stm32h7', self.config_stm32h7),
('', self.config_unknown)]
for name, func in cfg_funcs:
@ -146,6 +147,11 @@ class PrinterTemperatureMCU:
cal_adc_130 = self.read16(0x1FFF75CA) * 3.0 / (3.3 * 4095.)
self.slope = (130. - 30.) / (cal_adc_130 - cal_adc_30)
self.base_temperature = self.calc_base(30., cal_adc_30)
def config_stm32h723(self):
cal_adc_30 = self.read16(0x1FF1E820) / 4095.
cal_adc_130 = self.read16(0x1FF1E840) / 4095.
self.slope = (130. - 30.) / (cal_adc_130 - cal_adc_30)
self.base_temperature = self.calc_base(30., cal_adc_30)
def config_stm32h7(self):
cal_adc_30 = self.read16(0x1FF1E820) / 65535.
cal_adc_110 = self.read16(0x1FF1E840) / 65535.

10
src/stm32/Kconfig
View File

@ -71,6 +71,9 @@ choice
config MACH_STM32G431
bool "STM32G431"
select MACH_STM32G4
config MACH_STM32H723
bool "STM32H723"
select MACH_STM32H7
config MACH_STM32H743
bool "STM32H743"
select MACH_STM32H7
@ -141,6 +144,7 @@ config MCU
default "stm32f446xx" if MACH_STM32F446
default "stm32g0b1xx" if MACH_STM32G0B1
default "stm32g431xx" if MACH_STM32G431
default "stm32h723xx" if MACH_STM32H723
default "stm32h743xx" if MACH_STM32H743
default "stm32h750xx" if MACH_STM32H750
default "stm32l412xx" if MACH_STM32L412
@ -165,7 +169,7 @@ config FLASH_SIZE
default 0x8000 if MACH_STM32F042
default 0x20000 if MACH_STM32F070 || MACH_STM32F072
default 0x10000 if MACH_STM32F103 || MACH_STM32L412 # Flash size of stm32f103x8 (64KiB)
default 0x40000 if MACH_STM32F2 || MACH_STM32F401
default 0x40000 if MACH_STM32F2 || MACH_STM32F401 || MACH_STM32H723
default 0x80000 if MACH_STM32F4x5 || MACH_STM32F446
default 0x20000 if MACH_STM32G0B1 || MACH_STM32G431
default 0x20000 if MACH_STM32H750
@ -239,7 +243,7 @@ choice
config STM32_FLASH_START_4000
bool "16KiB bootloader (HID Bootloader)" if MACH_STM32F207 || MACH_STM32F401 || MACH_STM32F4x5 || MACH_STM32F103 || MACH_STM32F072
config STM32_FLASH_START_20000
bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743
bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723
config STM32_FLASH_START_0000
bool "No bootloader"
@ -318,7 +322,7 @@ choice
select USBSERIAL
config STM32_USB_PB14_PB15
bool "USB (on PB14/PB15)"
depends on MACH_STM32H7
depends on MACH_STM32H743 || MACH_STM32H750
select USBSERIAL
config STM32_SERIAL_USART1
bool "Serial (on USART1 PA10/PA9)"

7
src/stm32/stm32h7.c
View File

@ -83,10 +83,11 @@ DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
static void
clock_setup(void)
{
#if !CONFIG_MACH_STM32H723
// Ensure USB OTG ULPI is not enabled
CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);
CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN);
#endif
// Set this despite correct defaults.
// "The software has to program the supply configuration in PWR control
// register 3" (pg. 259)
@ -143,7 +144,11 @@ clock_setup(void)
// Enable VOS0 (overdrive)
if (CONFIG_CLOCK_FREQ > 400000000) {
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;
#if !CONFIG_MACH_STM32H723
SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN;
#else
PWR->CR3 |= PWR_CR3_BYPASS;
#endif
while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
;
}

119
src/stm32/stm32h7_adc.c
View File

@ -14,47 +14,50 @@
#include "sched.h" // sched_shutdown
#if CONFIG_MACH_STM32H7
#define ADCIN_BANK_SIZE (20)
#define RCC_AHBENR_ADC (RCC->AHB1ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB1ENR_ADC12EN)
#define ADC_CKMODE (0b11)
#define ADC_ATICKS (0b101)
#define ADC_RES (0b110)
#define ADC_TS (ADC3_COMMON)
#define ADCIN_BANK_SIZE (20)
#define RCC_AHBENR_ADC (RCC->AHB1ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB1ENR_ADC12EN)
#define ADC_CKMODE (0b11)
#define ADC_ATICKS (0b101)
#define ADC_RES (0b110)
#define ADC_TS (ADC3_COMMON)
#if CONFIG_MACH_STM32H723
#define PCSEL PCSEL_RES0
#endif
// Number of samples is 2^OVERSAMPLES_EXPONENT (exponent can be 0-10)
#define OVERSAMPLES_EXPONENT 3
#define OVERSAMPLES (1 << OVERSAMPLES_EXPONENT)
#define ADC_MEAS_DELAY (1 + 2.3666*OVERSAMPLES)
// Number of samples is 2^OVERSAMPLES_EXPONENT (exponent can be 0-10)
#define OVERSAMPLES_EXPONENT 3
#define OVERSAMPLES (1 << OVERSAMPLES_EXPONENT)
#define ADC_MEAS_DELAY (1 + 2.3666*OVERSAMPLES)
// LDORDY registers are missing from CMSIS (only available on revision V!)
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos)
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk
// LDORDY registers are missing from CMSIS (only available on revision V!)
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos)
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk
#elif CONFIG_MACH_STM32L4
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADCEN)
#define ADC_CKMODE (0)
#define ADC_ATICKS (0b100)
#define ADC_RES (0b00)
#define ADC_TS (ADC12_COMMON)
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADCEN)
#define ADC_CKMODE (0)
#define ADC_ATICKS (0b100)
#define ADC_RES (0b00)
#define ADC_TS (ADC12_COMMON)
#define OVERSAMPLES (0)
#define ADC_MEAS_DELAY (10)
#define OVERSAMPLES (0)
#define ADC_MEAS_DELAY (10)
#elif CONFIG_MACH_STM32G4
#define ADCIN_BANK_SIZE (19)
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADC12EN)
#define ADC_CKMODE (0b11)
#define ADC_ATICKS (0b100)
#define ADC_RES (0b00)
#define ADC_TS (ADC12_COMMON)
#define ADC_CCR_TSEN (ADC_CCR_VSENSESEL)
#define ADCIN_BANK_SIZE (19)
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADC12EN)
#define ADC_CKMODE (0b11)
#define ADC_ATICKS (0b100)
#define ADC_RES (0b00)
#define ADC_TS (ADC12_COMMON)
#define ADC_CCR_TSEN (ADC_CCR_VSENSESEL)
#define OVERSAMPLES (0)
#define ADC_MEAS_DELAY (10)
#define OVERSAMPLES (0)
#define ADC_MEAS_DELAY (10)
#endif
#define ADC_TEMPERATURE_PIN 0xfe
@ -126,8 +129,13 @@ static const uint8_t adc_pins[] = {
GPIO('H', 3), // ADC3_INP14
GPIO('H', 4), // ADC3_INP15
GPIO('H', 5), // ADC3_INP16
#if CONFIG_MACH_STM32H723
ADC_TEMPERATURE_PIN,
0,
#else
0, // Vbat/4
ADC_TEMPERATURE_PIN,// VSENSE
#endif
0, // VREFINT
#elif CONFIG_MACH_STM32G4
0, // [0] vssa
@ -239,20 +247,31 @@ gpio_adc_setup(uint32_t pin)
}
// Enable the ADC
if (!(adc->CR & ADC_CR_ADEN)){
if (!(adc->CR & ADC_CR_ADEN)) {
// STM32H723 ADC3 and ADC1/2 registers are slightly different
uint8_t is_stm32h723_adc3 = 0;
#if CONFIG_MACH_STM32H723
if (adc == ADC3) {
is_stm32h723_adc3 = 1;
}
#endif
// Pwr
// Exit deep power down
MODIFY_REG(adc->CR, ADC_CR_DEEPPWD_Msk, 0);
// Switch on voltage regulator
adc->CR |= ADC_CR_ADVREGEN;
#ifdef ADC_ISR_LDORDY
while(!(adc->ISR & ADC_ISR_LDORDY))
;
#else // stm32l4 lacks ldordy, delay to spec instead
uint32_t end = timer_read_time() + timer_from_us(20);
while (timer_is_before(timer_read_time(), end))
;
if (is_stm32h723_adc3 == 0) {
while(!(adc->ISR & ADC_ISR_LDORDY))
;
} else
#endif
{
// stm32h723 ADC3 & stm32l4 lacks ldordy, delay to spec instead
uint32_t end = timer_read_time() + timer_from_us(20);
while (timer_is_before(timer_read_time(), end))
;
}
// Set Boost mode for 25Mhz < ADC clock <= 50Mhz
#ifdef ADC_CR_BOOST
@ -295,12 +314,26 @@ gpio_adc_setup(uint32_t pin)
// Disable Continuous Mode
MODIFY_REG(adc->CFGR, ADC_CFGR_CONT_Msk, 0);
// Set to 12 bit
MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES << ADC_CFGR_RES_Pos);
if (is_stm32h723_adc3) {
#ifdef ADC3_CFGR_RES
MODIFY_REG(adc->CFGR, ADC3_CFGR_RES_Msk, 0 << ADC3_CFGR_RES_Pos);
MODIFY_REG(adc->CFGR, ADC3_CFGR_ALIGN_Msk, 0<<ADC3_CFGR_ALIGN_Pos);
#endif
} else {
MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES<<ADC_CFGR_RES_Pos);
}
#if CONFIG_MACH_STM32H7
// Set hardware oversampling
MODIFY_REG(adc->CFGR2, ADC_CFGR2_ROVSE_Msk, ADC_CFGR2_ROVSE);
MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSR_Msk,
(OVERSAMPLES - 1) << ADC_CFGR2_OVSR_Pos);
if (is_stm32h723_adc3) {
#ifdef ADC3_CFGR2_OVSR
MODIFY_REG(adc->CFGR2, ADC3_CFGR2_OVSR_Msk,
(OVERSAMPLES_EXPONENT - 1) << ADC3_CFGR2_OVSR_Pos);
#endif
} else {
MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSR_Msk,
(OVERSAMPLES - 1) << ADC_CFGR2_OVSR_Pos);
}
MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSS_Msk,
OVERSAMPLES_EXPONENT << ADC_CFGR2_OVSS_Pos);
#else // stm32l4

38
src/stm32/usbotg.c
View File

@ -15,21 +15,31 @@
#include "sched.h" // DECL_INIT
#if CONFIG_STM32_USB_PB14_PB15
#define USB_PERIPH_BASE USB_OTG_HS_PERIPH_BASE
#define OTG_IRQn OTG_HS_IRQn
#define USBOTGEN RCC_AHB1ENR_USB1OTGHSEN
#define GPIO_D_NEG GPIO('B', 14)
#define GPIO_D_POS GPIO('B', 15)
#define GPIO_FUNC GPIO_FUNCTION(12)
DECL_CONSTANT_STR("RESERVE_PINS_USB1", "PB14,PB15");
#define IS_OTG_HS 1
#define GPIO_D_NEG GPIO('B', 14)
#define GPIO_D_POS GPIO('B', 15)
#define GPIO_FUNC GPIO_FUNCTION(12)
DECL_CONSTANT_STR("RESERVE_PINS_USB1", "PB14,PB15");
#else
#define USB_PERIPH_BASE USB_OTG_FS_PERIPH_BASE
#define OTG_IRQn OTG_FS_IRQn
#define USBOTGEN RCC_AHB1ENR_USB2OTGHSEN
#define GPIO_D_NEG GPIO('A', 11)
#define GPIO_D_POS GPIO('A', 12)
#define GPIO_FUNC GPIO_FUNCTION(10)
DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12");
#if CONFIG_MACH_STM32H723
#define IS_OTG_HS 1
#else
#define IS_OTG_HS 0
#endif
#define GPIO_D_NEG GPIO('A', 11)
#define GPIO_D_POS GPIO('A', 12)
#define GPIO_FUNC GPIO_FUNCTION(10)
DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12");
#endif
#if IS_OTG_HS
#define USB_PERIPH_BASE USB_OTG_HS_PERIPH_BASE
#define OTG_IRQn OTG_HS_IRQn
#define USBOTGEN RCC_AHB1ENR_USB1OTGHSEN
#else
#define USB_PERIPH_BASE USB_OTG_FS_PERIPH_BASE
#define OTG_IRQn OTG_FS_IRQn
#define USBOTGEN RCC_AHB1ENR_USB2OTGHSEN
#endif
static void