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stm32: Expand stm32g0 family (#5838) 

Add stm32g07x family support.

Signed-off-by: Alex Voinea <voinea.dragos.alexandru@gmail.com>
This commit is contained in:
Alex Voinea 2023-01-03 19:43:46 +02:00 committed by GitHub
parent b337cc3ee8
commit 9c2ccceb9f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 62 additions and 25 deletions
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13
src/stm32/Kconfig
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@ -65,6 +65,14 @@ choice
bool "STM32F072" bool "STM32F072"
select MACH_STM32F0 select MACH_STM32F0
select MACH_STM32F0x2 select MACH_STM32F0x2
config MACH_STM32G070
bool "STM32G070"
select MACH_STM32G0
select MACH_STM32G07x
config MACH_STM32G071
bool "STM32G071"
select MACH_STM32G0
select MACH_STM32G07x
config MACH_STM32G0B0 config MACH_STM32G0B0
bool "STM32G0B0" bool "STM32G0B0"
select MACH_STM32G0 select MACH_STM32G0
@ -104,6 +112,8 @@ config MACH_STM32F4
bool bool
config MACH_STM32G0 config MACH_STM32G0
bool bool
config MACH_STM32G07x
bool
config MACH_STM32G0Bx config MACH_STM32G0Bx
bool bool
config MACH_STM32G4 config MACH_STM32G4
@ -149,6 +159,8 @@ config MCU
default "stm32f407xx" if MACH_STM32F407 default "stm32f407xx" if MACH_STM32F407
default "stm32f429xx" if MACH_STM32F429 default "stm32f429xx" if MACH_STM32F429
default "stm32f446xx" if MACH_STM32F446 default "stm32f446xx" if MACH_STM32F446
default "stm32g070xx" if MACH_STM32G070
default "stm32g071xx" if MACH_STM32G071
default "stm32g0b0xx" if MACH_STM32G0B0 default "stm32g0b0xx" if MACH_STM32G0B0
default "stm32g0b1xx" if MACH_STM32G0B1 default "stm32g0b1xx" if MACH_STM32G0B1
default "stm32g431xx" if MACH_STM32G431 default "stm32g431xx" if MACH_STM32G431
@ -203,6 +215,7 @@ config RAM_SIZE
default 0x20000 if MACH_STM32F207 default 0x20000 if MACH_STM32F207
default 0x10000 if MACH_STM32F401 default 0x10000 if MACH_STM32F401
default 0x20000 if MACH_STM32F4x5 || MACH_STM32F446 default 0x20000 if MACH_STM32F4x5 || MACH_STM32F446
default 0x9000 if MACH_STM32G07x
default 0x24000 if MACH_STM32G0Bx default 0x24000 if MACH_STM32G0Bx
default 0x20000 if MACH_STM32H7 default 0x20000 if MACH_STM32H7

4
src/stm32/hard_pwm.c
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@ -117,10 +117,12 @@ static const struct gpio_pwm_info pwm_regs[] = {
{TIM1, GPIO('B', 3), 2, GPIO_FUNCTION(1)}, {TIM1, GPIO('B', 3), 2, GPIO_FUNCTION(1)},
{TIM3, GPIO('B', 4), 1, GPIO_FUNCTION(1)}, {TIM3, GPIO('B', 4), 1, GPIO_FUNCTION(1)},
{TIM3, GPIO('B', 5), 2, GPIO_FUNCTION(1)}, {TIM3, GPIO('B', 5), 2, GPIO_FUNCTION(1)},
#if CONFIG_MACH_STM32G0Bx
{TIM4, GPIO('B', 6), 1, GPIO_FUNCTION(9)}, {TIM4, GPIO('B', 6), 1, GPIO_FUNCTION(9)},
{TIM4, GPIO('B', 7), 2, GPIO_FUNCTION(9)}, {TIM4, GPIO('B', 7), 2, GPIO_FUNCTION(9)},
{TIM4, GPIO('B', 8), 3, GPIO_FUNCTION(9)}, {TIM4, GPIO('B', 8), 3, GPIO_FUNCTION(9)},
{TIM4, GPIO('B', 9), 4, GPIO_FUNCTION(9)}, {TIM4, GPIO('B', 9), 4, GPIO_FUNCTION(9)},
#endif
{TIM15, GPIO('B', 14), 1, GPIO_FUNCTION(5)}, {TIM15, GPIO('B', 14), 1, GPIO_FUNCTION(5)},
{TIM15, GPIO('B', 15), 2, GPIO_FUNCTION(5)}, {TIM15, GPIO('B', 15), 2, GPIO_FUNCTION(5)},
{TIM15, GPIO('C', 1), 1, GPIO_FUNCTION(2)}, {TIM15, GPIO('C', 1), 1, GPIO_FUNCTION(2)},
@ -134,10 +136,12 @@ static const struct gpio_pwm_info pwm_regs[] = {
{TIM14, GPIO('C', 12), 1, GPIO_FUNCTION(2)}, {TIM14, GPIO('C', 12), 1, GPIO_FUNCTION(2)},
{TIM16, GPIO('D', 0), 1, GPIO_FUNCTION(2)}, {TIM16, GPIO('D', 0), 1, GPIO_FUNCTION(2)},
{TIM17, GPIO('D', 1), 1, GPIO_FUNCTION(2)}, {TIM17, GPIO('D', 1), 1, GPIO_FUNCTION(2)},
#if CONFIG_MACH_STM32G0Bx
{TIM4, GPIO('D', 12), 1, GPIO_FUNCTION(2)}, {TIM4, GPIO('D', 12), 1, GPIO_FUNCTION(2)},
{TIM4, GPIO('D', 13), 2, GPIO_FUNCTION(2)}, {TIM4, GPIO('D', 13), 2, GPIO_FUNCTION(2)},
{TIM4, GPIO('D', 14), 3, GPIO_FUNCTION(2)}, {TIM4, GPIO('D', 14), 3, GPIO_FUNCTION(2)},
{TIM4, GPIO('D', 15), 4, GPIO_FUNCTION(2)}, {TIM4, GPIO('D', 15), 4, GPIO_FUNCTION(2)},
#endif
{TIM3, GPIO('E', 3), 1, GPIO_FUNCTION(1)}, {TIM3, GPIO('E', 3), 1, GPIO_FUNCTION(1)},
{TIM3, GPIO('E', 4), 2, GPIO_FUNCTION(1)}, {TIM3, GPIO('E', 4), 2, GPIO_FUNCTION(1)},
{TIM3, GPIO('E', 5), 3, GPIO_FUNCTION(1)}, {TIM3, GPIO('E', 5), 3, GPIO_FUNCTION(1)},

57
src/stm32/stm32f0_i2c.c
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@ -27,27 +27,34 @@ DECL_ENUMERATION("i2c_bus", "i2c1", 0);
DECL_CONSTANT_STR("BUS_PINS_i2c1", "PB6,PB7"); DECL_CONSTANT_STR("BUS_PINS_i2c1", "PB6,PB7");
DECL_ENUMERATION("i2c_bus", "i2c1a", 1); DECL_ENUMERATION("i2c_bus", "i2c1a", 1);
DECL_CONSTANT_STR("BUS_PINS_i2c1a", "PF1,PF0"); DECL_CONSTANT_STR("BUS_PINS_i2c1a", "PF1,PF0");
#elif CONFIG_MACH_STM32G0
#elif CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4
DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0); DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7"); DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 1); DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 1);
DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9"); DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9");
#if CONFIG_MACH_STM32G0 DECL_ENUMERATION("i2c_bus", "i2c1_PA9_PA10", 2);
#define GPIO_AF_INDEX 6 DECL_CONSTANT_STR("BUS_PINS_i2c1_PA9_PA10", "PA9,PA10");
DECL_ENUMERATION("i2c_bus", "i2c3_PB3_PB4", 2);
DECL_CONSTANT_STR("BUS_PINS_i2c3_PB3_PB4", "PB3,PB4");
#elif CONFIG_MACH_STM32L4
#define GPIO_AF_INDEX 4
DECL_ENUMERATION("i2c_bus", "i2c3_PA7_PB4", 2);
DECL_CONSTANT_STR("BUS_PINS_i2c3_PA7_PB4", "PA7,PB4");
#endif
DECL_ENUMERATION("i2c_bus", "i2c2_PB10_PB11", 3); DECL_ENUMERATION("i2c_bus", "i2c2_PB10_PB11", 3);
DECL_CONSTANT_STR("BUS_PINS_i2c2_PB10_PB11", "PB10,PB11"); DECL_CONSTANT_STR("BUS_PINS_i2c2_PB10_PB11", "PB10,PB11");
DECL_ENUMERATION("i2c_bus", "i2c2_PB13_PB14", 4); DECL_ENUMERATION("i2c_bus", "i2c2_PB13_PB14", 4);
DECL_CONSTANT_STR("BUS_PINS_i2c2_PB13_PB14", "PB13,PB14"); DECL_CONSTANT_STR("BUS_PINS_i2c2_PB13_PB14", "PB13,PB14");
DECL_ENUMERATION("i2c_bus", "i2c1_PA9_PA10", 5); #ifdef I2C3
DECL_ENUMERATION("i2c_bus", "i2c3_PB3_PB4", 5);
DECL_CONSTANT_STR("BUS_PINS_i2c3_PB3_PB4", "PB3,PB4");
#endif
#elif CONFIG_MACH_STM32L4
DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
DECL_ENUMERATION("i2c_bus", "i2c1_PB8_PB9", 1);
DECL_CONSTANT_STR("BUS_PINS_i2c1_PB8_PB9", "PB8,PB9");
DECL_ENUMERATION("i2c_bus", "i2c1_PA9_PA10", 2);
DECL_CONSTANT_STR("BUS_PINS_i2c1_PA9_PA10", "PA9,PA10"); DECL_CONSTANT_STR("BUS_PINS_i2c1_PA9_PA10", "PA9,PA10");
DECL_ENUMERATION("i2c_bus", "i2c2_PB10_PB11", 3);
DECL_CONSTANT_STR("BUS_PINS_i2c2_PB10_PB11", "PB10,PB11");
DECL_ENUMERATION("i2c_bus", "i2c2_PB13_PB14", 4);
DECL_CONSTANT_STR("BUS_PINS_i2c2_PB13_PB14", "PB13,PB14");
DECL_ENUMERATION("i2c_bus", "i2c3_PA7_PB4", 5);
DECL_CONSTANT_STR("BUS_PINS_i2c3_PA7_PB4", "PA7,PB4");
#elif CONFIG_MACH_STM32G4 #elif CONFIG_MACH_STM32G4
DECL_ENUMERATION("i2c_bus", "i2c1_PA13_PA14", 0); DECL_ENUMERATION("i2c_bus", "i2c1_PA13_PA14", 0);
DECL_CONSTANT_STR("BUS_PINS_i2c1_PA13_PA14", "PA13,PA14"); DECL_CONSTANT_STR("BUS_PINS_i2c1_PA13_PA14", "PA13,PA14");
@ -72,18 +79,22 @@ static const struct i2c_info i2c_bus[] = {
{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) }, { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) },
{ I2C1, GPIO('F', 1), GPIO('F', 0), GPIO_FUNCTION(1) }, { I2C1, GPIO('F', 1), GPIO('F', 0), GPIO_FUNCTION(1) },
{ I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(1) }, { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(1) },
#elif CONFIG_MACH_STM32G0
#elif CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(6) },
{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(GPIO_AF_INDEX) }, { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(6) },
{ I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(GPIO_AF_INDEX) }, { I2C1, GPIO('A', 9), GPIO('A', 10), GPIO_FUNCTION(6) },
#if CONFIG_MACH_STM32G0 { I2C2, GPIO('B', 10), GPIO('B', 11), GPIO_FUNCTION(6) },
{ I2C3, GPIO('B', 3), GPIO('B', 4), GPIO_FUNCTION(GPIO_AF_INDEX) }, { I2C2, GPIO('B', 13), GPIO('B', 14), GPIO_FUNCTION(6) },
#elif CONFIG_MACH_STM32L4 #ifdef I2C3
{ I2C3, GPIO('A', 7), GPIO('B', 4), GPIO_FUNCTION(GPIO_AF_INDEX) }, { I2C3, GPIO('B', 3), GPIO('B', 4), GPIO_FUNCTION(6) },
#endif #endif
{ I2C2, GPIO('B', 10), GPIO('B', 11), GPIO_FUNCTION(GPIO_AF_INDEX) }, #elif CONFIG_MACH_STM32L4
{ I2C2, GPIO('B', 13), GPIO('B', 14), GPIO_FUNCTION(GPIO_AF_INDEX) }, { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(4) },
{ I2C1, GPIO('A', 9), GPIO('A', 10), GPIO_FUNCTION(GPIO_AF_INDEX) }, { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(4) },
{ I2C1, GPIO('A', 9), GPIO('A', 10), GPIO_FUNCTION(4) },
{ I2C2, GPIO('B', 10), GPIO('B', 11), GPIO_FUNCTION(4) },
{ I2C2, GPIO('B', 13), GPIO('B', 14), GPIO_FUNCTION(4) },
{ I2C3, GPIO('A', 7), GPIO('B', 4), GPIO_FUNCTION(4) },
#elif CONFIG_MACH_STM32G4 #elif CONFIG_MACH_STM32G4
{ I2C1, GPIO('A', 13), GPIO('A', 14), GPIO_FUNCTION(4) }, { I2C1, GPIO('A', 13), GPIO('A', 14), GPIO_FUNCTION(4) },
{ I2C1, GPIO('A', 15), GPIO('A', 14), GPIO_FUNCTION(4) }, { I2C1, GPIO('A', 15), GPIO('A', 14), GPIO_FUNCTION(4) },

13
src/stm32/stm32g0.c
View File

@ -36,14 +36,18 @@ lookup_clock_line(uint32_t periph_base)
if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE)) if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE))
return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12}; return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12};
#endif #endif
#ifdef USB_BASE
if (periph_base == USB_BASE) if (periph_base == USB_BASE)
return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13}; return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<13};
#endif
#ifdef CRS_BASE #ifdef CRS_BASE
if (periph_base == CRS_BASE) if (periph_base == CRS_BASE)
return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<16}; return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<16};
#endif #endif
#ifdef I2C3_BASE
if (periph_base == I2C3_BASE) if (periph_base == I2C3_BASE)
return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<23}; return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<23};
#endif
if (periph_base == TIM1_BASE) if (periph_base == TIM1_BASE)
return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<11}; return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<11};
if (periph_base == SPI1_BASE) if (periph_base == SPI1_BASE)
@ -106,8 +110,11 @@ clock_setup(void)
} }
pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos; pllcfgr |= (pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos;
pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos; pllcfgr |= (pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLLCFGR_PLLR_Pos;
pllcfgr |= (pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos; #ifdef RCC_PLLCFGR_PLLQ
RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN; pllcfgr |= ((pll_freq/FREQ_USB - 1) << RCC_PLLCFGR_PLLQ_Pos)
| RCC_PLLCFGR_PLLQEN;
#endif
RCC->PLLCFGR = pllcfgr | RCC_PLLCFGR_PLLREN;
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
// Wait for PLL lock // Wait for PLL lock
@ -119,8 +126,10 @@ clock_setup(void)
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != (2 << RCC_CFGR_SWS_Pos)) while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != (2 << RCC_CFGR_SWS_Pos))
; ;
#ifdef USB_BASE
// Use PLLQCLK for USB (setting USBSEL=2 works in practice) // Use PLLQCLK for USB (setting USBSEL=2 works in practice)
RCC->CCIPR2 = 2 << RCC_CCIPR2_USBSEL_Pos; RCC->CCIPR2 = 2 << RCC_CCIPR2_USBSEL_Pos;
#endif
} }