stm32f4: Add support for full range of GPIO pins
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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@ -1,10 +1,11 @@
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// Code to setup clocks on stm32f4
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// Code to setup clocks and gpio on stm32f4
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_STM32F4_CLOCK_REF_8M
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 4)
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@ -52,6 +53,33 @@ get_pclock_frequency(uint32_t periph_base)
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return FREQ_PERIPH;
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}
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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uint32_t rcc_pos = ((uint32_t)regs - AHB1PERIPH_BASE) / 0x400;
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RCC->AHB1ENR |= (1<<rcc_pos);
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// Configure GPIO
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uint32_t mode_bits = mode & 0x0f, func = mode >> 4;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift);
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}
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#if CONFIG_STM32F4_CLOCK_REF_8M
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
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#endif
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// Clock configuration
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static void
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enable_clock_stm32f40x(void)
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@ -127,9 +155,4 @@ clock_setup(void)
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RCC->CFGR = RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4 | RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
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;
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// Enable GPIO clocks
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enable_pclock(GPIOA_BASE);
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enable_pclock(GPIOB_BASE);
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enable_pclock(GPIOC_BASE);
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}
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@ -14,28 +14,22 @@
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DECL_ENUMERATION_RANGE("pin", "PA0", GPIO('A', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PB0", GPIO('B', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PC0", GPIO('C', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PD0", GPIO('D', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PE0", GPIO('E', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PF0", GPIO('F', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PG0", GPIO('G', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PH0", GPIO('H', 0), 32);
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#ifdef GPIOI
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DECL_ENUMERATION_RANGE("pin", "PI0", GPIO('I', 0), 32);
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#endif
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static GPIO_TypeDef * const digital_regs[] = {
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GPIOA, GPIOB, GPIOC
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GPIO_TypeDef * const digital_regs[] = {
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GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH,
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#ifdef GPIOI
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GPIOI,
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#endif
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};
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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uint32_t mode_bits = mode & 0x0f, func = mode >> 4;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift);
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}
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// Convert a register and bit location back to an integer pin identifier
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static int
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regs_to_pin(GPIO_TypeDef *regs, uint32_t bit)
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@ -47,11 +41,6 @@ regs_to_pin(GPIO_TypeDef *regs, uint32_t bit)
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return 0;
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}
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/****************************************************************
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* General Purpose Input Output (GPIO) pins
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****************************************************************/
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struct gpio_out
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gpio_out_setup(uint32_t pin, uint32_t val)
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{
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@ -4,6 +4,8 @@
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#include "stm32f4xx.h"
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extern GPIO_TypeDef * const digital_regs[];
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#define GPIO(PORT, NUM) (((PORT)-'A') * 16 + (NUM))
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#define GPIO2PORT(PIN) ((PIN) / 16)
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#define GPIO2BIT(PIN) (1<<((PIN) % 16))
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