stm32: Implement armcm_main() in arch specific code
Move armcm_main() to stm32f0.c, stm32f1.c, and stm32f4.c. This gives the arch specific code more control on the early boot setup. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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@ -22,7 +22,7 @@ CFLAGS_klipper.elf += -T $(OUT)src/generic/armcm_link.ld
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$(OUT)klipper.elf: $(OUT)src/generic/armcm_link.ld
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# Add source files
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src-y += stm32/main.c stm32/watchdog.c stm32/gpio.c generic/crc16_ccitt.c
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src-y += stm32/watchdog.c stm32/gpio.c generic/crc16_ccitt.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-$(CONFIG_MACH_STM32F0) += ../lib/stm32f0/system_stm32f0xx.c
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src-$(CONFIG_MACH_STM32F0) += generic/timer_irq.c stm32/stm32f0_timer.c
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@ -27,7 +27,6 @@ extern GPIO_TypeDef * const digital_regs[];
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void enable_pclock(uint32_t periph_base);
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int is_enabled_pclock(uint32_t periph_base);
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uint32_t get_pclock_frequency(uint32_t periph_base);
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void clock_setup(void);
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void gpio_clock_enable(GPIO_TypeDef *regs);
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void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup);
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@ -1,18 +0,0 @@
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// Main starting point for STM32 boards.
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/armcm_boot.h" // armcm_main
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#include "internal.h" // clock_setup
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#include "sched.h" // sched_main
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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SystemInit();
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clock_setup();
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sched_main();
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}
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@ -5,8 +5,10 @@
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_8M
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#include "board/armcm_boot.h" // armcm_main
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#include "sched.h" // sched_main
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#define FREQ_PERIPH 48000000
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@ -147,10 +149,12 @@ hsi48_setup(void)
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#endif
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}
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// Main clock setup called at chip startup
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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clock_setup(void)
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armcm_main(void)
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{
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SystemInit();
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// Set flash latency
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FLASH->ACR = (1 << FLASH_ACR_LATENCY_Pos) | FLASH_ACR_PRFTBE;
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@ -167,4 +171,6 @@ clock_setup(void)
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SYSCFG->CFGR1 |= SYSCFG_CFGR1_PA11_PA12_RMP;
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}
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#endif
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sched_main();
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}
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@ -9,6 +9,7 @@
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#include "board/irq.h" // irq_disable
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#include "board/usb_cdc.h" // usb_request_bootloader
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#include "internal.h" // enable_pclock
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#include "sched.h" // sched_main
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 2)
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@ -123,12 +124,9 @@ usb_request_bootloader(void)
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}
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// Main clock setup called at chip startup
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void
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static void
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clock_setup(void)
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{
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// The SystemInit() code alters VTOR - restore it
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SCB->VTOR = (uint32_t)VectorTable;
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// Configure and enable PLL
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uint32_t cfgr;
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if (CONFIG_CLOCK_REF_8M) {
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@ -157,8 +155,22 @@ clock_setup(void)
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RCC->CFGR = cfgr | RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
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;
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}
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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// Run SystemInit() and then restore VTOR
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SystemInit();
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SCB->VTOR = (uint32_t)VectorTable;
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// Setup clocks
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clock_setup();
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// Disable JTAG to free PA15, PB3, PB4
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enable_pclock(AFIO_BASE);
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AFIO->MAPR = AFIO_MAPR_SWJ_CFG_JTAGDISABLE;
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sched_main();
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}
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@ -9,6 +9,7 @@
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#include "board/usb_cdc.h" // usb_request_bootloader
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#include "sched.h" // sched_main
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 4)
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@ -174,12 +175,9 @@ enable_clock_stm32f446(void)
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}
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// Main clock setup called at chip startup
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void
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static void
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clock_setup(void)
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{
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// The SystemInit() code alters VTOR - restore it
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SCB->VTOR = (uint32_t)VectorTable;
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// Configure and enable PLL
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if (CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407)
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enable_clock_stm32f40x();
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@ -199,3 +197,16 @@ clock_setup(void)
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
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;
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}
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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// Run SystemInit() and then restore VTOR
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SystemInit();
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SCB->VTOR = (uint32_t)VectorTable;
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clock_setup();
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sched_main();
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}
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