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stm32: Support PA11/PA12 and PB8/PB9 on fdcan 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2022-06-10 22:48:53 -04:00
parent ce186c6af6
commit 913c6a913d
2 changed files with 20 additions and 16 deletions
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4
src/stm32/Kconfig
View File

@ -322,7 +322,7 @@ choice
select SERIAL select SERIAL
config STM32_CANBUS_PA11_PA12 config STM32_CANBUS_PA11_PA12
bool "CAN bus (on PA11/PA12)" bool "CAN bus (on PA11/PA12)"
depends on HAVE_STM32_CANBUS depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS
select CANSERIAL select CANSERIAL
config STM32_CANBUS_PA11_PA12_REMAP config STM32_CANBUS_PA11_PA12_REMAP
bool "CAN bus (on PA9/PA10)" if LOW_LEVEL_OPTIONS bool "CAN bus (on PA9/PA10)" if LOW_LEVEL_OPTIONS
@ -330,7 +330,7 @@ choice
select CANSERIAL select CANSERIAL
config STM32_CANBUS_PB8_PB9 config STM32_CANBUS_PB8_PB9
bool "CAN bus (on PB8/PB9)" if LOW_LEVEL_OPTIONS bool "CAN bus (on PB8/PB9)" if LOW_LEVEL_OPTIONS
depends on HAVE_STM32_CANBUS depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS
select CANSERIAL select CANSERIAL
config STM32_CANBUS_PI9_PH13 config STM32_CANBUS_PI9_PH13
bool "CAN bus (on PI9/PH13)" if LOW_LEVEL_OPTIONS bool "CAN bus (on PI9/PH13)" if LOW_LEVEL_OPTIONS

32
src/stm32/fdcan.c
View File

@ -61,24 +61,31 @@ FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE);
#define FDCAN_IE_TC (FDCAN_IE_TCE | FDCAN_IE_TCFE | FDCAN_IE_TFEE) #define FDCAN_IE_TC (FDCAN_IE_TCE | FDCAN_IE_TCFE | FDCAN_IE_TFEE)
#if CONFIG_STM32_CANBUS_PB0_PB1 #if CONFIG_STM32_CANBUS_PA11_PA12
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PA11,PA12");
#define GPIO_Rx GPIO('A', 11)
#define GPIO_Tx GPIO('A', 12)
#elif CONFIG_STM32_CANBUS_PB8_PB9
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB8,PB9");
#define GPIO_Rx GPIO('B', 8)
#define GPIO_Tx GPIO('B', 9)
#elif CONFIG_STM32_CANBUS_PB0_PB1
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB0,PB1"); DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB0,PB1");
#define GPIO_Rx GPIO('B', 0) #define GPIO_Rx GPIO('B', 0)
#define GPIO_Tx GPIO('B', 1) #define GPIO_Tx GPIO('B', 1)
#endif #endif
#if CONFIG_MACH_STM32G0 #if !CONFIG_STM32_CANBUS_PB0_PB1
#if CONFIG_STM32_CANBUS_PB0_PB1 #define SOC_CAN FDCAN1
#define SOC_CAN FDCAN2 #define MSG_RAM fdcan_ram->fdcan1
#define MSG_RAM fdcan_ram->fdcan2 #else
#else #define SOC_CAN FDCAN2
#error Uknown pins for STMF32G0 CAN #define MSG_RAM fdcan_ram->fdcan2
#endif
#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
#endif #endif
#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn
#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number
#ifndef SOC_CAN #ifndef SOC_CAN
#error No known CAN device for configured MCU #error No known CAN device for configured MCU
#endif #endif
@ -240,9 +247,6 @@ can_init(void)
/* Enable configuration change */ /* Enable configuration change */
SOC_CAN->CCCR |= FDCAN_CCCR_CCE; SOC_CAN->CCCR |= FDCAN_CCCR_CCE;
if (SOC_CAN == FDCAN1)
FDCAN_CONFIG->CKDIV = 0;
/* Disable protocol exception handling */ /* Disable protocol exception handling */
SOC_CAN->CCCR |= FDCAN_CCCR_PXHD; SOC_CAN->CCCR |= FDCAN_CCCR_PXHD;