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stm32: Update can.c to use more consistent indentation 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2021-01-27 18:29:12 -05:00
parent 7d4df65920
commit 901ccfcb9d
1 changed files with 143 additions and 146 deletions
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143
src/stm32/can.c
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@ -1,49 +1,47 @@
/*
* Serial over CAN emulation for STM32 boards.
*
* Copyright (C) 2019 Eug Krashtan <eug.krashtan@gmail.com>
* Copyright (C) 2020 Pontus Borg <glpontus@gmail.com>
* This file may be distributed under the terms of the GNU GPLv3 license.
*
*/
// Serial over CAN emulation for STM32 boards.
//
// Copyright (C) 2019 Eug Krashtan <eug.krashtan@gmail.com>
// Copyright (C) 2020 Pontus Borg <glpontus@gmail.com>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include "autoconf.h" //
#include "board/armcm_boot.h" // armcm_enable_irq
#include "board/serial_irq.h" // serial_rx_byte
#include <string.h> // memcpy
#include "autoconf.h" // CONFIG_MACH_STM32F1
#include "can.h" // SHORT_UUID_LEN
#include "command.h" // DECL_CONSTANT_STR
#include "fasthash.h" // fasthash64
#include "generic/armcm_boot.h" // armcm_enable_irq
#include "generic/serial_irq.h" // serial_rx_byte
#include "internal.h" // enable_pclock
#include "sched.h" // DECL_INIT
#include <string.h>
#include "can.h"
#include <fasthash.h>
#if (CONFIG_CAN_PINS_PA11_PA12)
#if CONFIG_CAN_PINS_PA11_PA12
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PA11,PA12");
#define GPIO_Rx GPIO('A', 11)
#define GPIO_Tx GPIO('A', 12)
#endif
#if (CONFIG_CAN_PINS_PB8_PB9)
#if CONFIG_CAN_PINS_PB8_PB9
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB8,PB9");
#define GPIO_Rx GPIO('B', 8)
#define GPIO_Tx GPIO('B', 9)
#endif
#if (CONFIG_CAN_PINS_PI8_PH13)
#if CONFIG_CAN_PINS_PI8_PH13
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PI8,PH13");
#define GPIO_Rx GPIO('I', 8)
#define GPIO_Tx GPIO('H', 13)
#endif
#if (CONFIG_CAN_PINS_PB5_PB6)
#if CONFIG_CAN_PINS_PB5_PB6
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB5,PB6");
#define GPIO_Rx GPIO('B', 5)
#define GPIO_Tx GPIO('B', 6)
#endif
#if (CONFIG_CAN_PINS_PB12_PB13)
#if CONFIG_CAN_PINS_PB12_PB13
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
#define GPIO_Rx GPIO('B', 12)
#define GPIO_Tx GPIO('B', 13)
#endif
#if (CONFIG_MACH_STM32F0)
#if CONFIG_MACH_STM32F0
#define SOC_CAN CAN
#define CAN_RX0_IRQn CEC_CAN_IRQn
#define CAN_RX1_IRQn CEC_CAN_IRQn
@ -52,7 +50,7 @@ DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
#define CAN_FUNCTION GPIO_FUNCTION(4) // Alternative function mapping number
#endif
#if (CONFIG_MACH_STM32F1)
#if CONFIG_MACH_STM32F1
#define SOC_CAN CAN1
#define CAN_RX0_IRQn CAN1_RX0_IRQn
#define CAN_RX1_IRQn CAN1_RX1_IRQn
@ -61,18 +59,16 @@ DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
#define CAN_FUNCTION GPIO_FUNCTION(9) // Alternative function mapping number
#endif
#if (CONFIG_MACH_STM32F4)
#if CONFIG_MACH_STM32F4
#warning CAN on STM32F4 is untested
#if (CONFIG_CAN_PINS_PA11_PA12 || \
CONFIG_CAN_PINS_PB8_PB9 || \
CONFIG_CAN_PINS_PI8_PH13)
#if (CONFIG_CAN_PINS_PA11_PA12 || CONFIG_CAN_PINS_PB8_PB9 \
|| CONFIG_CAN_PINS_PI8_PH13)
#define SOC_CAN CAN1
#define CAN_RX0_IRQn CAN1_RX0_IRQn
#define CAN_RX1_IRQn CAN1_RX1_IRQn
#define CAN_TX_IRQn CAN1_TX_IRQn
#define CAN_SCE_IRQn CAN1_SCE_IRQn
#elif ((CONFIG_CAN_PINS_PB5_PB6 || CONFIG_CAN_PINS_PB12_PB13)
#elif CONFIG_CAN_PINS_PB5_PB6 || CONFIG_CAN_PINS_PB12_PB13
#define SOC_CAN CAN2
#define CAN_RX0_IRQn CAN2_RX0_IRQn
#define CAN_RX1_IRQn CAN2_RX1_IRQn
@ -85,12 +81,10 @@ DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
#define CAN_FUNCTION GPIO_FUNCTION(9) // Alternative function mapping number
#endif
#ifndef SOC_CAN
#error No known CAN device for configured MCU
#endif
// TXFP makes packets posted to the TX mboxes transmit in chronologcal order
// ABOM makes the hardware automatically leave bus-off state
#define MCR_FLAGS (CAN_MCR_TXFP | CAN_MCR_ABOM)
@ -99,15 +93,21 @@ DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
static uint16_t MyCanId = 0;
static int can_find_empty_tx_mbox(void) {
static int
can_find_empty_tx_mbox(void)
{
uint32_t tsr = SOC_CAN->TSR;
if(tsr & CAN_TSR_TME0) return 0;
if(tsr & CAN_TSR_TME1) return 1;
if(tsr & CAN_TSR_TME2) return 2;
if (tsr & CAN_TSR_TME0)
return 0;
if (tsr & CAN_TSR_TME1)
return 1;
if (tsr & CAN_TSR_TME2)
return 2;
return -1;
}
static void can_transmit_mbox(uint32_t id, int mbox, uint32_t dlc, uint8_t *pkt)
static void
can_transmit_mbox(uint32_t id, int mbox, uint32_t dlc, uint8_t *pkt)
{
CAN_TxMailBox_TypeDef *mb = &SOC_CAN->sTxMailBox[mbox];
/* Set up the Id */
@ -120,25 +120,25 @@ static void can_transmit_mbox(uint32_t id, int mbox, uint32_t dlc, uint8_t *pkt)
/* Set up the data field */
if (pkt) {
mb->TDLR = ((uint32_t)pkt[3] << 24) |
((uint32_t)pkt[2] << 16) |
((uint32_t)pkt[1] << 8) |
((uint32_t)pkt[0] << 0);
mb->TDHR = ((uint32_t)pkt[7] << 24) |
((uint32_t)pkt[6] << 16) |
((uint32_t)pkt[5] << 8) |
((uint32_t)pkt[4] << 0);
mb->TDLR = (((uint32_t)pkt[3] << 24)
| ((uint32_t)pkt[2] << 16)
| ((uint32_t)pkt[1] << 8)
| ((uint32_t)pkt[0] << 0));
mb->TDHR = (((uint32_t)pkt[7] << 24)
| ((uint32_t)pkt[6] << 16)
| ((uint32_t)pkt[5] << 8)
| ((uint32_t)pkt[4] << 0));
}
/* Request transmission */
__sync_synchronize(); // disable write optimization
mb->TIR |= CAN_TI0R_TXRQ;
}
// Blocking transmit function, it can race with the IRQ driven TX handler.
// This should(tm) not happen
static void can_transmit(uint32_t id, uint32_t dlc, uint8_t *pkt)
static void
can_transmit(uint32_t id, uint32_t dlc, uint8_t *pkt)
{
int mbox = -1;
@ -150,20 +150,23 @@ static void can_transmit(uint32_t id, uint32_t dlc, uint8_t *pkt)
}
// Convert Unique 96-bit value into 48 bit representation
static void pack_uuid(uint8_t* u)
static void
pack_uuid(uint8_t *u)
{
uint64_t hash = fasthash64((uint8_t*)UID_BASE, 12, 0xA16231A7);
memcpy(u, &hash, SHORT_UUID_LEN);
}
static void can_uuid_resp(void)
static void
can_uuid_resp(void)
{
uint8_t short_uuid[SHORT_UUID_LEN];
pack_uuid(short_uuid);
can_transmit(PKT_ID_UUID_RESP, SHORT_UUID_LEN, short_uuid);
}
static void get_rx_data(uint8_t* buf, unsigned int mbox)
static void
get_rx_data(uint8_t *buf, unsigned int mbox)
{
uint32_t rdlr = SOC_CAN->sFIFOMailBox[mbox].RDLR;
buf[0] = (rdlr >> 0) & 0xff;
@ -178,7 +181,9 @@ static void get_rx_data(uint8_t* buf, unsigned int mbox)
}
// Return true if more data is available to send or mailboxes are full
int CAN_TxIrq(void) {
static int
CAN_TxIrq(void)
{
int txdata = 1;
// TODO: We need some kind of error handling?
@ -189,10 +194,9 @@ int CAN_TxIrq(void) {
// All mboxes full, wait for next IRQ
return 1;
}
int i=0;
int i;
uint8_t databuf[8];
for (;i<8;i++)
{
for (i=0; i<8; i++) {
if (serial_get_tx_byte(&(databuf[i])) == -1) {
txdata = 0;
break;
@ -205,7 +209,8 @@ int CAN_TxIrq(void) {
return txdata;
}
void CAN_RxCpltCallback(unsigned int mbox)
static void
CAN_RxCpltCallback(unsigned int mbox)
{
CAN_FIFOMailBox_TypeDef *mb = &SOC_CAN->sFIFOMailBox[mbox];
uint32_t id = (mb->RIR >> CAN_RI0R_STID_Pos) & 0x7FF;
@ -251,12 +256,9 @@ void CAN_RxCpltCallback(unsigned int mbox)
serial_rx_byte(databuf[i]);
}
}
}
else if (id == PKT_ID_UUID && dlc > 0)
{
} else if (id == PKT_ID_UUID && dlc > 0) {
get_rx_data(databuf, mbox);
if (memcmp(databuf, &MyCanId, 2) == 0)
{
if (memcmp(databuf, &MyCanId, 2) == 0) {
// Reset from host
NVIC_SystemReset();
}
@ -264,9 +266,7 @@ void CAN_RxCpltCallback(unsigned int mbox)
}
}
/**
* @brief This function handles CAN global interrupts
*/
// This function handles CAN global interrupts
void
CAN_IRQHandler(void)
{
@ -287,14 +287,12 @@ CAN_IRQHandler(void)
}
/* Check Overrun flag for FIFO0 */
if(SOC_CAN->RF0R & CAN_RF0R_FOVR0)
{
if (SOC_CAN->RF0R & CAN_RF0R_FOVR0) {
/* Clear FIFO0 Overrun Flag */
SOC_CAN->RF0R |= CAN_RF0R_FOVR0;
}
/* Check Overrun flag for FIFO1 */
if(SOC_CAN->RF1R & CAN_RF1R_FOVR1)
{
if (SOC_CAN->RF1R & CAN_RF1R_FOVR1) {
/* Clear FIFO1 Overrun Flag */
SOC_CAN->RF1R |= CAN_RF1R_FOVR1;
}
@ -312,17 +310,15 @@ make_btr(uint32_t sjw, // Sync jump width, ... hmm
uint32_t time_seg2, // time segment after sample point, 1 .. 8
uint32_t brp) // Baud rate prescaler, 1 .. 1024
{
return
((uint32_t)(sjw-1)) << CAN_BTR_SJW_Pos
return (((uint32_t)(sjw-1)) << CAN_BTR_SJW_Pos
| ((uint32_t)(time_seg1-1)) << CAN_BTR_TS1_Pos
| ((uint32_t)(time_seg2-1)) << CAN_BTR_TS2_Pos
| ((uint32_t)(brp - 1)) << CAN_BTR_BRP_Pos;
| ((uint32_t)(brp - 1)) << CAN_BTR_BRP_Pos);
}
static inline const uint32_t
compute_btr(uint32_t pclock, uint32_t bitrate) {
compute_btr(uint32_t pclock, uint32_t bitrate)
{
/*
Some equations:
Tpclock = 1 / pclock
@ -375,7 +371,8 @@ can_init(void)
/* Request initialisation */
SOC_CAN->MCR |= CAN_MCR_INRQ;
/* Wait the acknowledge */
while( !(SOC_CAN->MSR & CAN_MSR_INAK) );
while (!(SOC_CAN->MSR & CAN_MSR_INAK))
;
SOC_CAN->MCR |= MCR_FLAGS;
SOC_CAN->BTR = btr;
@ -383,7 +380,8 @@ can_init(void)
/* Request leave initialisation */
SOC_CAN->MCR &= ~(CAN_MCR_INRQ);
/* Wait the acknowledge */
while( SOC_CAN->MSR & CAN_MSR_INAK );
while (SOC_CAN->MSR & CAN_MSR_INAK)
;
/*##-2- Configure the CAN Filter #######################################*/
uint32_t filternbrbitpos = (1U) << CAN_FILTER_NUMBER;
@ -422,7 +420,6 @@ can_init(void)
armcm_enable_irq(CAN_IRQHandler, CAN_TX_IRQn, 0);
// TODO: CAN_SCE_IRQ?n
/*##-4- Say Hello #################################*/
can_uuid_resp();
}