rp2040: Fix watchdog enable
The rp2040 watchdog does not actually reset anything by default. The psm_hw->wdsel field must be programmed to actually get a reset on a watchdog failure. Program that field so the watchdog is usable. Also, disable the watchdog before attempting a reboot into the bootloader. Otherwise the machine may just reboot a second time due to a missed watchdog event in the bootloader. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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@ -9,6 +9,7 @@
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#include "generic/armcm_reset.h" // try_request_canboot
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#include "generic/armcm_reset.h" // try_request_canboot
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#include "hardware/structs/clocks.h" // clock_hw_t
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#include "hardware/structs/clocks.h" // clock_hw_t
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#include "hardware/structs/pll.h" // pll_hw_t
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#include "hardware/structs/pll.h" // pll_hw_t
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#include "hardware/structs/psm.h" // psm_hw
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#include "hardware/structs/resets.h" // sio_hw
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#include "hardware/structs/resets.h" // sio_hw
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#include "hardware/structs/watchdog.h" // watchdog_hw
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#include "hardware/structs/watchdog.h" // watchdog_hw
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#include "hardware/structs/xosc.h" // xosc_hw
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#include "hardware/structs/xosc.h" // xosc_hw
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@ -30,6 +31,7 @@ DECL_TASK(watchdog_reset);
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void
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void
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watchdog_init(void)
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watchdog_init(void)
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{
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{
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psm_hw->wdsel = PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS|PSM_WDSEL_XOSC_BITS);
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watchdog_reset();
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watchdog_reset();
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watchdog_hw->ctrl = (WATCHDOG_CTRL_PAUSE_DBG0_BITS
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watchdog_hw->ctrl = (WATCHDOG_CTRL_PAUSE_DBG0_BITS
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| WATCHDOG_CTRL_PAUSE_DBG1_BITS
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| WATCHDOG_CTRL_PAUSE_DBG1_BITS
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@ -46,6 +48,7 @@ DECL_INIT(watchdog_init);
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void
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void
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bootloader_request(void)
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bootloader_request(void)
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{
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{
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watchdog_hw->ctrl = 0;
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try_request_canboot();
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try_request_canboot();
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// Use the bootrom-provided code to reset into BOOTSEL mode
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// Use the bootrom-provided code to reset into BOOTSEL mode
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reset_to_usb_boot(0, 0);
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reset_to_usb_boot(0, 0);
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