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stm32: Enable 48Mhz USB clock on stm32f446 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2019-08-12 09:37:21 -04:00
parent effe6f6ddd
commit 841150ff00
1 changed files with 22 additions and 0 deletions
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22
src/stm32/stm32f4.c
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@ -131,6 +131,28 @@ enable_clock_stm32f446(void)
PWR->CR = (3 << PWR_CR_VOS_Pos) | PWR_CR_ODEN | PWR_CR_ODSWEN; PWR->CR = (3 << PWR_CR_VOS_Pos) | PWR_CR_ODEN | PWR_CR_ODSWEN;
while (!(PWR->CSR & PWR_CSR_ODSWRDY)) while (!(PWR->CSR & PWR_CSR_ODSWRDY))
; ;
// Enable 48Mhz USB clock
if (CONFIG_USBSERIAL) {
if (CONFIG_CLOCK_REF_8M) {
RCC->PLLSAICFGR = (
(4 << RCC_PLLSAICFGR_PLLSAIM_Pos)
| (96 << RCC_PLLSAICFGR_PLLSAIN_Pos)
| (1 << RCC_PLLSAICFGR_PLLSAIP_Pos)
| (4 << RCC_PLLSAICFGR_PLLSAIQ_Pos));
} else {
RCC->PLLSAICFGR = (
(8 << RCC_PLLSAICFGR_PLLSAIM_Pos)
| (96 << RCC_PLLSAICFGR_PLLSAIN_Pos)
| (1 << RCC_PLLSAICFGR_PLLSAIP_Pos)
| (4 << RCC_PLLSAICFGR_PLLSAIQ_Pos));
}
RCC->CR |= RCC_CR_PLLSAION;
while (!(RCC->CR & RCC_CR_PLLSAIRDY))
;
RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL;
}
#endif #endif
} }