From 841150ff007556e13664716d5ad0cdf7507d0482 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Mon, 12 Aug 2019 09:37:21 -0400 Subject: [PATCH] stm32: Enable 48Mhz USB clock on stm32f446 Signed-off-by: Kevin O'Connor --- src/stm32/stm32f4.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index d0a2f249..dab8d524 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -131,6 +131,28 @@ enable_clock_stm32f446(void) PWR->CR = (3 << PWR_CR_VOS_Pos) | PWR_CR_ODEN | PWR_CR_ODSWEN; while (!(PWR->CSR & PWR_CSR_ODSWRDY)) ; + + // Enable 48Mhz USB clock + if (CONFIG_USBSERIAL) { + if (CONFIG_CLOCK_REF_8M) { + RCC->PLLSAICFGR = ( + (4 << RCC_PLLSAICFGR_PLLSAIM_Pos) + | (96 << RCC_PLLSAICFGR_PLLSAIN_Pos) + | (1 << RCC_PLLSAICFGR_PLLSAIP_Pos) + | (4 << RCC_PLLSAICFGR_PLLSAIQ_Pos)); + } else { + RCC->PLLSAICFGR = ( + (8 << RCC_PLLSAICFGR_PLLSAIM_Pos) + | (96 << RCC_PLLSAICFGR_PLLSAIN_Pos) + | (1 << RCC_PLLSAICFGR_PLLSAIP_Pos) + | (4 << RCC_PLLSAICFGR_PLLSAIQ_Pos)); + } + RCC->CR |= RCC_CR_PLLSAION; + while (!(RCC->CR & RCC_CR_PLLSAIRDY)) + ; + + RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL; + } #endif }