stm32f4: Add support for STM32F103
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
KevinOConnor
parent
485164b8b3
commit
7efc53ff59
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@ -16,32 +16,47 @@ config BOARD_DIRECTORY
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choice
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prompt "Processor model"
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config MACH_STM32F103
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bool "STM32F103"
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select MACH_STM32F1xx
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config MACH_STM32F405
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bool "STM32F405"
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select MACH_STM32F4xx
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config MACH_STM32F407
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bool "STM32F407"
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select MACH_STM32F4xx
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config MACH_STM32F446
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bool "STM32F446"
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select MACH_STM32F4xx
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endchoice
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config MACH_STM32F1xx
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bool
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config MACH_STM32F4xx
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bool
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config MCU
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string
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default "stm32f405" if MACH_STM32F405
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default "stm32f407" if MACH_STM32F407
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default "stm32f446" if MACH_STM32F446
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default "stm32f103xb" if MACH_STM32F103
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default "stm32f405xx" if MACH_STM32F405
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default "stm32f407xx" if MACH_STM32F407
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default "stm32f446xx" if MACH_STM32F446
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config CLOCK_FREQ
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int
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default 72000000 if MACH_STM32F103
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default 168000000 if MACH_STM32F405 || MACH_STM32F407
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default 180000000 if MACH_STM32F446
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config FLASH_SIZE
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hex
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default 0x10000 if MACH_STM32F103
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default 0x80000 if MACH_STM32F405 || MACH_STM32F407
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default 0x80000 if MACH_STM32F446
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config RAM_SIZE
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hex
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default 0x5000 if MACH_STM32F103
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default 0x30000 if MACH_STM32F405 || MACH_STM32F407
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default 0x20000 if MACH_STM32F446
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@ -4,20 +4,26 @@
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CROSS_PREFIX=arm-none-eabi-
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dirs-y += src/stm32f4 src/generic
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dirs-y += lib/stm32f4 lib/stm32f4/gcc
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dirs-$(CONFIG_MACH_STM32F1xx) += lib/stm32f1 lib/stm32f1/gcc
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dirs-$(CONFIG_MACH_STM32F4xx) += lib/stm32f4 lib/stm32f4/gcc
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MCU := $(shell echo $(CONFIG_MCU) | tr a-z A-Z)
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CFLAGS += -D$(MCU)xx
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MCU := $(shell echo $(CONFIG_MCU))
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MCU_UPPER := $(shell echo $(CONFIG_MCU) | tr a-z A-Z | tr X x)
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CFLAGS += -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
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CFLAGS += -Ilib/cmsis-core -Ilib/stm32f4/include
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CFLAGS-$(CONFIG_MACH_STM32F1xx) += -mcpu=cortex-m3 -Ilib/stm32f1/include
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CFLAGS-$(CONFIG_MACH_STM32F4xx) += -mcpu=cortex-m4 -Ilib/stm32f4/include
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CFLAGS-$(CONFIG_MACH_STM32F4xx) += -mfpu=fpv4-sp-d16 -mfloat-abi=hard
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CFLAGS += $(CFLAGS-y) -D$(MCU_UPPER) -mthumb -Ilib/cmsis-core
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CFLAGS_klipper.elf += -T $(OUT)stm32f4.ld --specs=nano.specs --specs=nosys.specs
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# Add source files
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src-y += stm32f4/main.c stm32f4/clock.c stm32f4/watchdog.c stm32f4/gpio.c
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src-y += stm32f4/main.c stm32f4/watchdog.c stm32f4/gpio.c
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src-y += generic/crc16_ccitt.c generic/armcm_irq.c generic/armcm_timer.c
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src-y += ../lib/stm32f4/system_stm32f4xx.c
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src-$(CONFIG_MACH_STM32F1xx) += ../lib/stm32f1/system_stm32f1xx.c
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src-$(CONFIG_MACH_STM32F1xx) += stm32f4/stm32f1.c
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src-$(CONFIG_MACH_STM32F4xx) += ../lib/stm32f4/system_stm32f4xx.c
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src-$(CONFIG_MACH_STM32F4xx) += stm32f4/clock.c
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src-$(CONFIG_HAVE_GPIO_ADC) += stm32f4/adc.c
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src-$(CONFIG_HAVE_GPIO_SPI) += stm32f4/spi.c
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src-$(CONFIG_SERIAL) += stm32f4/serial.c generic/serial_irq.c
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@ -27,7 +33,8 @@ $(OUT)%.o: %.s $(OUT)autoconf.h $(OUT)board-link
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@echo " Assembling $@"
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$(Q)$(AS) $< -o $@
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asmsrc-y := ../lib/stm32f4/gcc/startup_$(shell echo $(CONFIG_MCU))xx.s
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asmsrc-$(CONFIG_MACH_STM32F1xx) := ../lib/stm32f1/gcc/startup_$(MCU).s
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asmsrc-$(CONFIG_MACH_STM32F4xx) := ../lib/stm32f4/gcc/startup_$(MCU).s
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OBJS_klipper.elf += $(patsubst %.s, $(OUT)src/%.o,$(asmsrc-y))
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# Build the linker script
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@ -8,6 +8,7 @@
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#include "board/misc.h" // timer_from_us
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#include "command.h" // shutdown
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#include "compiler.h" // ARRAY_SIZE
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#include "generic/armcm_timer.h" // udelay
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#include "gpio.h" // gpio_adc_setup
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#include "internal.h" // GPIO
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#include "sched.h" // sched_shutdown
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@ -21,6 +22,12 @@ static const uint8_t adc_pins[] = {
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GPIO('C', 2), GPIO('C', 3), GPIO('C', 4), GPIO('C', 5)
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};
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#if CONFIG_MACH_STM32F1xx
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#define CR2_FLAGS (ADC_CR2_ADON | (7 << ADC_CR2_EXTSEL_Pos) | ADC_CR2_EXTTRIG)
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#else
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#define CR2_FLAGS ADC_CR2_ADON
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#endif
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struct gpio_adc
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gpio_adc_setup(uint32_t pin)
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{
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@ -36,14 +43,22 @@ gpio_adc_setup(uint32_t pin)
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// Enable the ADC
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if (!is_enabled_pclock(ADC1_BASE)) {
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enable_pclock(ADC1_BASE);
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uint32_t aticks = 3; // 56 adc cycles
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uint32_t aticks = 3; // 2.5-3.2us (depending on stm32 chip)
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ADC1->SMPR1 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9)
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| (aticks << 12) | (aticks << 15) | (aticks << 18)
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| (aticks << 21) | (aticks << 24));
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ADC1->SMPR2 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9)
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| (aticks << 12) | (aticks << 15) | (aticks << 18)
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| (aticks << 21) | (aticks << 24) | (aticks << 27));
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ADC1->CR2 = ADC_CR2_ADON;
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ADC1->CR2 = CR2_FLAGS;
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#if CONFIG_MACH_STM32F1xx
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// Perform calibration
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udelay(timer_from_us(1));
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ADC1->CR2 = ADC_CR2_CAL | CR2_FLAGS;
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while (ADC1->CR2 & ADC_CR2_CAL)
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;
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#endif
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}
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gpio_peripheral(pin, GPIO_ANALOG, 0);
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@ -67,9 +82,10 @@ gpio_adc_sample(struct gpio_adc g)
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}
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// Start sample
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ADC1->SQR3 = g.chan;
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ADC1->CR2 = ADC_CR2_SWSTART | ADC_CR2_ADON;
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ADC1->CR2 = ADC_CR2_SWSTART | CR2_FLAGS;
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need_delay:
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return timer_from_us(4);
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return timer_from_us(10);
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}
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// Read a value; use only after gpio_adc_sample() returns zero
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@ -16,15 +16,20 @@ DECL_ENUMERATION_RANGE("pin", "PB0", GPIO('B', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PC0", GPIO('C', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PD0", GPIO('D', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PE0", GPIO('E', 0), 32);
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#ifdef GPIOH
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DECL_ENUMERATION_RANGE("pin", "PF0", GPIO('F', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PG0", GPIO('G', 0), 32);
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DECL_ENUMERATION_RANGE("pin", "PH0", GPIO('H', 0), 32);
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#endif
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#ifdef GPIOI
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DECL_ENUMERATION_RANGE("pin", "PI0", GPIO('I', 0), 32);
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#endif
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GPIO_TypeDef * const digital_regs[] = {
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GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH,
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GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
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#ifdef GPIOH
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GPIOF, GPIOG, GPIOH,
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#endif
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#ifdef GPIOI
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GPIOI,
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#endif
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@ -2,7 +2,13 @@
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#define __STM32F4_INTERNAL_H
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// Local definitions for STM32F4 code
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#include "autoconf.h" // CONFIG_MACH_STM32F1xx
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#if CONFIG_MACH_STM32F1xx
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#include "stm32f1xx.h"
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#else
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#include "stm32f4xx.h"
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#endif
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extern GPIO_TypeDef * const digital_regs[];
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@ -0,0 +1,125 @@
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// Code to setup clocks and gpio on stm32f1
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_8M
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#include "internal.h" // enable_pclock
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 2)
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// Enable a peripheral clock
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void
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enable_pclock(uint32_t periph_base)
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{
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if (periph_base < APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
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RCC->APB1ENR |= (1<<pos);
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RCC->APB1ENR;
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} else if (periph_base < AHBPERIPH_BASE) {
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uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
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RCC->APB2ENR |= (1<<pos);
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RCC->APB2ENR;
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} else {
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uint32_t pos = (periph_base - AHBPERIPH_BASE) / 0x400;
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RCC->AHBENR |= (1<<pos);
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RCC->AHBENR;
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}
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}
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// Check if a peripheral clock has been enabled
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int
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is_enabled_pclock(uint32_t periph_base)
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{
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if (periph_base < APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
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return RCC->APB1ENR & (1<<pos);
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} else if (periph_base < AHBPERIPH_BASE) {
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uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
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return RCC->APB2ENR & (1<<pos);
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} else {
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uint32_t pos = (periph_base - AHBPERIPH_BASE) / 0x400;
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return RCC->AHBENR & (1<<pos);
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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uint32_t rcc_pos = ((uint32_t)regs - APB2PERIPH_BASE) / 0x400;
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RCC->APB2ENR |= 1 << rcc_pos;
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// Configure GPIO
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uint32_t pos = gpio % 16, shift = (pos % 8) * 4, msk = 0xf << shift, cfg;
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if (mode == GPIO_INPUT) {
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cfg = pullup ? 0x8 : 0x4;
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} else if (mode == GPIO_OUTPUT) {
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cfg = 0x1;
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} else if (mode == GPIO_ANALOG) {
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cfg = 0x0;
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} else {
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if (pullup > 0)
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// Alternate function input pins use GPIO_INPUT mode on the stm32f1
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cfg = 0x8;
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else
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cfg = 0x9;
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}
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if (pos & 0x8)
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regs->CRH = (regs->CRH & ~msk) | (cfg << shift);
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else
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regs->CRL = (regs->CRL & ~msk) | (cfg << shift);
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if (pullup > 0)
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regs->BSRR = 1 << pos;
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else if (pullup < 0)
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regs->BSRR = 1 << (pos + 16);
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}
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// Main clock setup called at chip startup
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void
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clock_setup(void)
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{
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uint32_t cfgr;
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if (CONFIG_CLOCK_REF_8M) {
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// Configure 72Mhz PLL from external 8Mhz crystal (HSE)
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RCC->CR |= RCC_CR_HSEON;
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cfgr = ((1 << RCC_CFGR_PLLSRC_Pos) | ((9 - 2) << RCC_CFGR_PLLMULL_Pos)
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| RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2
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| RCC_CFGR_ADCPRE_DIV4);
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} else {
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// Configure 72Mhz PLL from internal 8Mhz oscillator (HSI)
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cfgr = ((0 << RCC_CFGR_PLLSRC_Pos) | ((18 - 2) << RCC_CFGR_PLLMULL_Pos)
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| RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2
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| RCC_CFGR_ADCPRE_DIV4);
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}
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RCC->CFGR = cfgr;
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RCC->CR |= RCC_CR_PLLON;
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// Set flash latency
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FLASH->ACR = (2 << FLASH_ACR_LATENCY_Pos) | FLASH_ACR_PRFTBE;
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// Wait for PLL lock
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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// Switch system clock to PLL
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RCC->CFGR = cfgr | RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
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;
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// Disable JTAG to free PA15, PB3, PB4
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enable_pclock(AFIO_BASE);
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AFIO->MAPR = AFIO_MAPR_SWJ_CFG_JTAGDISABLE;
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}
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@ -19,7 +19,7 @@ watchdog_init(void)
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{
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IWDG->KR = 0x5555;
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IWDG->PR = 0;
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IWDG->RLR = 0x0FFF; // 512ms timeout
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IWDG->RLR = 0x0FFF; // 410-512ms timeout (depending on stm32 chip)
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IWDG->KR = 0xCCCC;
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}
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DECL_INIT(watchdog_init);
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