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atsamd: Increase ADC frequency on SAMD51 

The SAMD51 ADC is only clocked on rising edges (vs both rising and
falling edges on the SAMD21) and it has a greater minimum frequency
than the SAMD21.  So, increase the ADC clock.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2019-02-20 19:06:33 -05:00
parent ebc80ecea4
commit 7a32860455
1 changed files with 2 additions and 2 deletions
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4
src/atsamd/adc.c
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@ -108,14 +108,14 @@ adc_init(void)
while(ADC0->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL); while(ADC0->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL);
ADC0->SAMPCTRL.reg = ADC_SAMPCTRL_SAMPLEN(63); ADC0->SAMPCTRL.reg = ADC_SAMPCTRL_SAMPLEN(63);
while (ADC0->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL); while (ADC0->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL);
ADC0->CTRLA.reg = ADC_CTRLA_PRESCALER(ADC_CTRLA_PRESCALER_DIV128_Val) | ADC_CTRLA_ENABLE; ADC0->CTRLA.reg = ADC_CTRLA_PRESCALER(ADC_CTRLA_PRESCALER_DIV32_Val) | ADC_CTRLA_ENABLE;
// ADC1 // ADC1
ADC1->REFCTRL.reg = ADC_REFCTRL_REFSEL_INTVCC1; ADC1->REFCTRL.reg = ADC_REFCTRL_REFSEL_INTVCC1;
while(ADC1->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL); while(ADC1->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL);
ADC1->SAMPCTRL.reg = ADC_SAMPCTRL_SAMPLEN(63); ADC1->SAMPCTRL.reg = ADC_SAMPCTRL_SAMPLEN(63);
while(ADC1->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL); while(ADC1->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL);
ADC1->CTRLA.reg = ADC_CTRLA_PRESCALER(ADC_CTRLA_PRESCALER_DIV128_Val) | ADC_CTRLA_ENABLE; ADC1->CTRLA.reg = ADC_CTRLA_PRESCALER(ADC_CTRLA_PRESCALER_DIV32_Val) | ADC_CTRLA_ENABLE;
#endif #endif
} }