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stm32: Fix CAN for STM32G4 

Signed-off-by: Alex Maclean <monkeh@monkeh.net>
This commit is contained in:
Alex Maclean 2023-12-18 01:05:06 +00:00 committed by KevinOConnor
parent 147492b253
commit 77619e912c
2 changed files with 6 additions and 3 deletions
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6
src/stm32/fdcan.c
View File

@ -162,10 +162,10 @@ canhw_set_filter(uint32_t id)
can_filter(1, id); can_filter(1, id);
can_filter(2, id + 1); can_filter(2, id + 1);
#if CONFIG_MACH_STM32G0 #if CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32G4
SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos
| 0x02 << FDCAN_RXGFC_ANFS_Pos); | 0x02 << FDCAN_RXGFC_ANFS_Pos);
#elif CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4 #elif CONFIG_MACH_STM32H7
uint32_t flssa = (uint32_t)MSG_RAM.FLS - SRAMCAN_BASE; uint32_t flssa = (uint32_t)MSG_RAM.FLS - SRAMCAN_BASE;
SOC_CAN->SIDFC = flssa | ((id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos); SOC_CAN->SIDFC = flssa | ((id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos);
SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos; SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos;
@ -293,7 +293,7 @@ can_init(void)
SOC_CAN->NBTP = btr; SOC_CAN->NBTP = btr;
#if CONFIG_MACH_STM32H7 || CONFIG_MAC_STM32G4 #if CONFIG_MACH_STM32H7
/* Setup message RAM addresses */ /* Setup message RAM addresses */
uint32_t f0sa = (uint32_t)MSG_RAM.RXF0 - SRAMCAN_BASE; uint32_t f0sa = (uint32_t)MSG_RAM.RXF0 - SRAMCAN_BASE;
SOC_CAN->RXF0C = f0sa | (ARRAY_SIZE(MSG_RAM.RXF0) << FDCAN_RXF0C_F0S_Pos); SOC_CAN->RXF0C = f0sa | (ARRAY_SIZE(MSG_RAM.RXF0) << FDCAN_RXF0C_F0S_Pos);

3
src/stm32/stm32g4.c
View File

@ -105,6 +105,9 @@ enable_clock_stm32g4(void)
enable_pclock(CRS_BASE); enable_pclock(CRS_BASE);
CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
} }
// Use PCLK for FDCAN
RCC->CCIPR = 2 << RCC_CCIPR_FDCANSEL_Pos;
} }
// Main clock setup called at chip startup // Main clock setup called at chip startup