samd21: Initial support for SAMD21 micro-controllers
Add initial support for the Atmel SAMD21 micro-controllers. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
71db5fbe31
commit
74cf4dc9e0
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@ -8,6 +8,8 @@ choice
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bool "Atmega AVR"
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bool "Atmega AVR"
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config MACH_SAM3X8E
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config MACH_SAM3X8E
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bool "SAM3x8e (Arduino Due)"
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bool "SAM3x8e (Arduino Due)"
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config MACH_SAMD21
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bool "SAMD21 (Arduino Zero)"
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config MACH_LPC176X
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config MACH_LPC176X
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bool "LPC176x (Smoothieboard)"
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bool "LPC176x (Smoothieboard)"
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config MACH_STM32F1
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config MACH_STM32F1
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@ -22,6 +24,7 @@ endchoice
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source "src/avr/Kconfig"
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source "src/avr/Kconfig"
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source "src/sam3x8e/Kconfig"
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source "src/sam3x8e/Kconfig"
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source "src/samd21/Kconfig"
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source "src/lpc176x/Kconfig"
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source "src/lpc176x/Kconfig"
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source "src/stm32f1/Kconfig"
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source "src/stm32f1/Kconfig"
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source "src/pru/Kconfig"
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source "src/pru/Kconfig"
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@ -0,0 +1,41 @@
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# Kconfig settings for SAMD21 processors
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if MACH_SAMD21
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config SAMD_SELECT
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bool
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default y
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config BOARD_DIRECTORY
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string
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default "samd21"
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config CLOCK_FREQ
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int
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default 48000000
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choice
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prompt "Bootloader offset"
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config FLASH_START_0000
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bool "No bootloader"
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config FLASH_START_2000
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bool "2K bootloader (Arduino Zero)"
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config FLASH_START_4000
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bool "4K bootloader (Arduino M0)"
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endchoice
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config FLASH_START
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hex
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default 0x4000 if FLASH_START_4000
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default 0x2000 if FLASH_START_2000
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default 0x0000
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config SERIAL
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bool
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default y
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config SERIAL_BAUD
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depends on SERIAL
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int "Baud rate for serial port"
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default 250000
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endif
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@ -0,0 +1,43 @@
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# Additional samd21 build rules
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# Setup the toolchain
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CROSS_PREFIX=arm-none-eabi-
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dirs-y += src/samd21 src/generic
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dirs-y += lib/samd21/samd21a/gcc/gcc/
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CFLAGS += -mthumb -mcpu=cortex-m0plus
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CFLAGS += -Ilib/cmsis-core -Ilib/samd21/samd21a/include
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CFLAGS += -D__SAMD21G18A__
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CFLAGS_klipper.elf += -T $(OUT)samd21.ld
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CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs
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# Add source files
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src-y += samd21/main.c samd21/timer.c samd21/clock.c samd21/gpio.c
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src-y += generic/crc16_ccitt.c generic/alloc.c
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src-y += generic/armcm_irq.c generic/timer_irq.c
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src-y += ../lib/samd21/samd21a/gcc/gcc/startup_samd21.c
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src-$(CONFIG_SERIAL) += samd21/serial.c generic/serial_irq.c
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# Support bootloader offset address
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target-y := $(OUT)samd21.ld $(target-y)
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$(OUT)samd21.ld: lib/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld $(OUT)board-link
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@echo " Preprocessing $@"
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$(Q)$(CPP) -P -MD -MT $@ -DFLASH_START=$(CONFIG_FLASH_START) $< -o $@
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# Build the additional hex and bin output files
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target-y += $(OUT)klipper.bin $(OUT)klipper.elf.hex
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$(OUT)klipper.bin: $(OUT)klipper.elf
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@echo " Creating hex file $@"
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$(Q)$(OBJCOPY) -O binary $< $@
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$(OUT)klipper.elf.hex: $(OUT)klipper.elf
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@echo " Creating hex file $@"
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$(Q)$(OBJCOPY) -j .text -j .relocate -O ihex $< $@
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flash: $(OUT)klipper.bin
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@echo ""
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@echo " The SAMD21 build does not currently support 'make flash'"
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@ -0,0 +1,73 @@
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// Code to setup peripheral clocks on the SAMD21
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//
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// Copyright (C) 2018 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_FREQ
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#include "compiler.h" // DIV_ROUND_CLOSEST
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#include "internal.h" // enable_pclock
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#include "samd21.h" // GCLK
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void
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enable_pclock(uint32_t clock_id, uint32_t pmask)
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{
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(clock_id) | GCLK_CLKCTRL_GEN_GCLK0
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| GCLK_CLKCTRL_CLKEN);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
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;
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PM->APBCMASK.reg |= pmask;
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}
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#define CLK_MAIN 0
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#define CLK_32K 1
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#define MCLK_DFLL48M 0
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#define CLK_32K_FREQ 32768
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void
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SystemInit(void)
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{
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// Setup flash to work with 48Mhz clock
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS_HALF;
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// Enable external 32Khz crystal
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uint32_t val = (SYSCTRL_XOSC32K_STARTUP(6)
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| SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K);
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SYSCTRL->XOSC32K.reg = val;
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SYSCTRL->XOSC32K.reg = val | SYSCTRL_XOSC32K_ENABLE;
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while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY))
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;
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// Reset GCLK
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GCLK->CTRL.reg = GCLK_CTRL_SWRST;
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while (GCLK->CTRL.reg & GCLK_CTRL_SWRST)
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;
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// Route 32Khz clock to DFLL48M
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLK_32K);
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLK_32K)
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| GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_GENEN);
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(MCLK_DFLL48M)
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| GCLK_CLKCTRL_GEN(CLK_32K) | GCLK_CLKCTRL_CLKEN);
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// Configure DFLL48M clock
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SYSCTRL->DFLLCTRL.reg = 0;
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uint32_t mul = DIV_ROUND_CLOSEST(CONFIG_CLOCK_FREQ, CLK_32K_FREQ);
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SYSCTRL->DFLLMUL.reg = (SYSCTRL_DFLLMUL_CSTEP(31)
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| SYSCTRL_DFLLMUL_FSTEP(511)
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| SYSCTRL_DFLLMUL_MUL(mul));
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SYSCTRL->DFLLCTRL.reg = (SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK
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| SYSCTRL_DFLLCTRL_QLDIS
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| SYSCTRL_DFLLCTRL_ENABLE);
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uint32_t ready = (SYSCTRL_PCLKSR_DFLLRDY | SYSCTRL_PCLKSR_DFLLLCKC
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| SYSCTRL_PCLKSR_DFLLLCKF);
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while ((SYSCTRL->PCLKSR.reg & ready) != ready)
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;
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// Switch main clock to DFLL48M clock
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLK_MAIN);
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLK_MAIN)
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| GCLK_GENCTRL_SRC_DFLL48M
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| GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN);
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}
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@ -0,0 +1,22 @@
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// samd21 gpio functions
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//
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// Copyright (C) 2018 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "internal.h" // gpio_peripheral
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#include "samd21.h" // PORT
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void
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gpio_peripheral(char bank, uint32_t bit, char ptype, uint32_t pull_up)
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{
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int group = bank == 'A' ? 0 : 1;
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PortGroup *pg = &PORT->Group[group];
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if (ptype) {
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volatile uint8_t *pmux = &pg->PMUX[bit/2].reg;
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uint8_t shift = (bit & 1) ? 4 : 0, mask = ~(0xf << shift);
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*pmux = (*pmux & mask) | ((ptype - 'A') << shift);
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}
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pg->PINCFG[bit].reg = ((ptype ? PORT_PINCFG_PMUXEN : 0)
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| (pull_up ? PORT_PINCFG_PULLEN : 0));
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}
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#ifndef __SAMD21_INTERNAL_H
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#define __SAMD21_INTERNAL_H
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// Local definitions for samd21 code
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#include <stdint.h> // uint32_t
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void enable_pclock(uint32_t clock_id, uint32_t pmask);
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void gpio_peripheral(char bank, uint32_t bit, char ptype, uint32_t pull_up);
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#endif // internal.h
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// Main starting point for SAMD21 boards
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//
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// Copyright (C) 2018 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "command.h" // DECL_CONSTANT
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#include "samd21.h" // SystemInit
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#include "sched.h" // sched_main
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DECL_CONSTANT(MCU, "samd21g");
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/****************************************************************
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* misc functions
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****************************************************************/
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void
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command_reset(uint32_t *args)
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{
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NVIC_SystemReset();
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}
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DECL_COMMAND_FLAGS(command_reset, HF_IN_SHUTDOWN, "reset");
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// Main entry point
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int
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main(void)
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{
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SystemInit();
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sched_main();
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return 0;
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}
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// samd21 serial port
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//
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// Copyright (C) 2018 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_SERIAL_BAUD
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#include "board/serial_irq.h" // serial_rx_data
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#include "internal.h" // enable_pclock
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#include "samd21.h" // SERCOM0
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#include "sched.h" // DECL_INIT
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void
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serial_init(void)
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{
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// Enable serial clock
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enable_pclock(SERCOM0_GCLK_ID_CORE, PM_APBCMASK_SERCOM0);
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// Enable pins
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gpio_peripheral('A', 10, 'C', 0);
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gpio_peripheral('A', 11, 'C', 0);
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// Configure serial
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SercomUsart *su = &SERCOM0->USART;
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su->CTRLA.reg = 0;
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uint32_t areg = (SERCOM_USART_CTRLA_MODE_USART_INT_CLK
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| SERCOM_USART_CTRLA_DORD
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| SERCOM_USART_CTRLA_SAMPR(1)
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| SERCOM_USART_CTRLA_TXPO(1)
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| SERCOM_USART_CTRLA_RXPO(3));
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su->CTRLA.reg = areg;
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su->CTRLB.reg = SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN;
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uint32_t baud8 = CONFIG_CLOCK_FREQ / (2 * CONFIG_SERIAL_BAUD);
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su->BAUD.reg = (SERCOM_USART_BAUD_FRAC_BAUD(baud8 / 8)
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| SERCOM_USART_BAUD_FRAC_FP(baud8 % 8));
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NVIC_SetPriority(SERCOM0_IRQn, 0);
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NVIC_EnableIRQ(SERCOM0_IRQn);
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su->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
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su->CTRLA.reg = areg | SERCOM_USART_CTRLA_ENABLE;
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}
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DECL_INIT(serial_init);
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void __visible
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SERCOM0_Handler(void)
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{
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uint32_t status = SERCOM0->USART.INTFLAG.reg;
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if (status & SERCOM_USART_INTFLAG_RXC)
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serial_rx_byte(SERCOM0->USART.DATA.reg);
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if (status & SERCOM_USART_INTFLAG_DRE) {
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uint8_t data;
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int ret = serial_get_tx_byte(&data);
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if (ret)
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SERCOM0->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
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else
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SERCOM0->USART.DATA.reg = data;
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}
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}
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void
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serial_enable_tx_irq(void)
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{
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SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
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}
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// SAMD21 timer interrupt scheduling
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//
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// Copyright (C) 2018 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/irq.h" // irq_disable
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#include "board/misc.h" // timer_read_time
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#include "board/timer_irq.h" // timer_dispatch_many
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#include "internal.h" // enable_pclock
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#include "samd21.h" // TC4
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#include "sched.h" // DECL_INIT
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// Set the next irq time
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static void
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timer_set(uint32_t value)
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{
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TC4->COUNT32.CC[0].reg = value;
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TC4->COUNT32.INTFLAG.reg = TC_INTFLAG_MC0;
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}
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// Return the current time (in absolute clock ticks).
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uint32_t
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timer_read_time(void)
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{
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return TC4->COUNT32.COUNT.reg;
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}
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// Activate timer dispatch as soon as possible
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void
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timer_kick(void)
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{
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timer_set(timer_read_time() + 50);
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}
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void
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timer_init(void)
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{
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// Supply power and clock to the timer
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enable_pclock(TC3_GCLK_ID, PM_APBCMASK_TC3);
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enable_pclock(TC4_GCLK_ID, PM_APBCMASK_TC4);
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// Configure the timer
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TcCount32 *tc = &TC4->COUNT32;
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irqstatus_t flag = irq_save();
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tc->CTRLA.reg = 0;
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tc->CTRLA.reg = TC_CTRLA_MODE_COUNT32;
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NVIC_SetPriority(TC4_IRQn, 2);
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||||||
|
NVIC_EnableIRQ(TC4_IRQn);
|
||||||
|
TC4->COUNT32.INTENSET.reg = TC_INTENSET_MC0;
|
||||||
|
TC4->COUNT32.COUNT.reg = 0;
|
||||||
|
timer_kick();
|
||||||
|
tc->CTRLA.reg = TC_CTRLA_MODE_COUNT32 | TC_CTRLA_ENABLE;
|
||||||
|
irq_restore(flag);
|
||||||
|
}
|
||||||
|
DECL_INIT(timer_init);
|
||||||
|
|
||||||
|
// IRQ handler
|
||||||
|
void __visible __aligned(16) // aligning helps stabilize perf benchmarks
|
||||||
|
TC4_Handler(void)
|
||||||
|
{
|
||||||
|
irq_disable();
|
||||||
|
uint32_t next = timer_dispatch_many();
|
||||||
|
timer_set(next);
|
||||||
|
irq_enable();
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue