lib: Add atmel same51 and same54 build definitions
This also replaces the samd51 component files with the definitions from the same54 repository. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
960fd0b1f3
commit
69bd26b757
10
lib/README
10
lib/README
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@ -31,6 +31,16 @@ Atmel.SAMD51_DFP.1.1.96.atpack zip file found at:
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http://packs.download.atmel.com/
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version 1.1.96 (extracted on 20190110).
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The same51 directory contains code from the
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Atmel.SAME51_DFP.1.1.139.atpack zip file found at:
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http://packs.download.atmel.com/
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version 1.1.139 (extracted on 20220929).
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The same54 directory contains code from the
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Atmel.SAME54_DFP.1.1.134.atpack zip file found at:
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http://packs.download.atmel.com/
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version 1.1.134 (extracted on 20221005).
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The same70b directory contains code from the
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Atmel.SAME70_DFP.2.4.166.atpack zip file found at:
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http://packs.download.atmel.com/
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@ -0,0 +1,52 @@
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/**
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* \file
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*
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* \brief Top level header file
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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#ifndef _SAM_
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#define _SAM_
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#if defined(__SAME51G19A__) || defined(__ATSAME51G19A__)
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#include "same51g19a.h"
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#elif defined(__SAME51G18A__) || defined(__ATSAME51G18A__)
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#include "same51g18a.h"
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#elif defined(__SAME51N20A__) || defined(__ATSAME51N20A__)
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#include "same51n20a.h"
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#elif defined(__SAME51N19A__) || defined(__ATSAME51N19A__)
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#include "same51n19a.h"
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#elif defined(__SAME51J19A__) || defined(__ATSAME51J19A__)
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#include "same51j19a.h"
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#elif defined(__SAME51J18A__) || defined(__ATSAME51J18A__)
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#include "same51j18a.h"
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#elif defined(__SAME51J20A__) || defined(__ATSAME51J20A__)
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#include "same51j20a.h"
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#else
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#error Library does not support the specified device
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#endif
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#endif /* _SAM_ */
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@ -0,0 +1,56 @@
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/**
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* \file
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*
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* \brief Top header file for SAME51
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAME51_
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#define _SAME51_
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/**
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* \defgroup SAME51_definitions SAME51 Device Definitions
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* \brief SAME51 CMSIS Definitions.
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*/
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#if defined(__SAME51G18A__) || defined(__ATSAME51G18A__)
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#include "same51g18a.h"
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#elif defined(__SAME51G19A__) || defined(__ATSAME51G19A__)
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#include "same51g19a.h"
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#elif defined(__SAME51J18A__) || defined(__ATSAME51J18A__)
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#include "same51j18a.h"
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#elif defined(__SAME51J19A__) || defined(__ATSAME51J19A__)
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#include "same51j19a.h"
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#elif defined(__SAME51J20A__) || defined(__ATSAME51J20A__)
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#include "same51j20a.h"
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#elif defined(__SAME51N19A__) || defined(__ATSAME51N19A__)
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#include "same51n19a.h"
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#elif defined(__SAME51N20A__) || defined(__ATSAME51N20A__)
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#include "same51n20a.h"
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#else
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#error Library does not support the specified device.
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#endif
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#endif /* _SAME51_ */
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@ -0,0 +1,985 @@
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/**
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* \file
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*
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* \brief Header file for SAME51G18A
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAME51G18A_
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#define _SAME51G18A_
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/**
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* \ingroup SAME51_definitions
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* \addtogroup SAME51G18A_definitions SAME51G18A definitions
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* This file defines all structures and symbols for SAME51G18A:
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* - registers and bitfields
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* - peripheral base address
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* - peripheral ID
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* - PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#include <stdint.h>
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#ifndef __cplusplus
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typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#else
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typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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#endif
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typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
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typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
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typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
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#endif
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#if !defined(SKIP_INTEGER_LITERALS)
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#if defined(_U_) || defined(_L_) || defined(_UL_)
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#error "Integer Literals macros already defined elsewhere"
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
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#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
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#define _L_(x) x ## L /**< C code: Long integer literal constant value */
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#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
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#else /* Assembler */
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#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
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#define _L_(x) x /**< Assembler: Long integer literal constant value */
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#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* SKIP_INTEGER_LITERALS */
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/* ************************************************************************** */
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/** CMSIS DEFINITIONS FOR SAME51G18A */
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/* ************************************************************************** */
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/** \defgroup SAME51G18A_cmsis CMSIS Definitions */
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/*@{*/
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M4 Processor Exceptions Numbers *******************/
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NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */
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BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
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/****** SAME51G18A-specific Interrupt Numbers *********************/
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PM_IRQn = 0, /**< 0 SAME51G18A Power Manager (PM) */
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MCLK_IRQn = 1, /**< 1 SAME51G18A Main Clock (MCLK) */
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OSCCTRL_0_IRQn = 2, /**< 2 SAME51G18A Oscillators Control (OSCCTRL) IRQ 0 */
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OSCCTRL_1_IRQn = 3, /**< 3 SAME51G18A Oscillators Control (OSCCTRL) IRQ 1 */
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OSCCTRL_2_IRQn = 4, /**< 4 SAME51G18A Oscillators Control (OSCCTRL) IRQ 2 */
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OSCCTRL_3_IRQn = 5, /**< 5 SAME51G18A Oscillators Control (OSCCTRL) IRQ 3 */
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OSCCTRL_4_IRQn = 6, /**< 6 SAME51G18A Oscillators Control (OSCCTRL) IRQ 4 */
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OSC32KCTRL_IRQn = 7, /**< 7 SAME51G18A 32kHz Oscillators Control (OSC32KCTRL) */
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SUPC_0_IRQn = 8, /**< 8 SAME51G18A Supply Controller (SUPC) IRQ 0 */
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SUPC_1_IRQn = 9, /**< 9 SAME51G18A Supply Controller (SUPC) IRQ 1 */
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WDT_IRQn = 10, /**< 10 SAME51G18A Watchdog Timer (WDT) */
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RTC_IRQn = 11, /**< 11 SAME51G18A Real-Time Counter (RTC) */
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EIC_0_IRQn = 12, /**< 12 SAME51G18A External Interrupt Controller (EIC) IRQ 0 */
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EIC_1_IRQn = 13, /**< 13 SAME51G18A External Interrupt Controller (EIC) IRQ 1 */
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EIC_2_IRQn = 14, /**< 14 SAME51G18A External Interrupt Controller (EIC) IRQ 2 */
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EIC_3_IRQn = 15, /**< 15 SAME51G18A External Interrupt Controller (EIC) IRQ 3 */
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EIC_4_IRQn = 16, /**< 16 SAME51G18A External Interrupt Controller (EIC) IRQ 4 */
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EIC_5_IRQn = 17, /**< 17 SAME51G18A External Interrupt Controller (EIC) IRQ 5 */
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EIC_6_IRQn = 18, /**< 18 SAME51G18A External Interrupt Controller (EIC) IRQ 6 */
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EIC_7_IRQn = 19, /**< 19 SAME51G18A External Interrupt Controller (EIC) IRQ 7 */
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EIC_8_IRQn = 20, /**< 20 SAME51G18A External Interrupt Controller (EIC) IRQ 8 */
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EIC_9_IRQn = 21, /**< 21 SAME51G18A External Interrupt Controller (EIC) IRQ 9 */
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EIC_10_IRQn = 22, /**< 22 SAME51G18A External Interrupt Controller (EIC) IRQ 10 */
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EIC_11_IRQn = 23, /**< 23 SAME51G18A External Interrupt Controller (EIC) IRQ 11 */
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EIC_12_IRQn = 24, /**< 24 SAME51G18A External Interrupt Controller (EIC) IRQ 12 */
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EIC_13_IRQn = 25, /**< 25 SAME51G18A External Interrupt Controller (EIC) IRQ 13 */
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EIC_14_IRQn = 26, /**< 26 SAME51G18A External Interrupt Controller (EIC) IRQ 14 */
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EIC_15_IRQn = 27, /**< 27 SAME51G18A External Interrupt Controller (EIC) IRQ 15 */
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FREQM_IRQn = 28, /**< 28 SAME51G18A Frequency Meter (FREQM) */
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NVMCTRL_0_IRQn = 29, /**< 29 SAME51G18A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
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NVMCTRL_1_IRQn = 30, /**< 30 SAME51G18A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
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DMAC_0_IRQn = 31, /**< 31 SAME51G18A Direct Memory Access Controller (DMAC) IRQ 0 */
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DMAC_1_IRQn = 32, /**< 32 SAME51G18A Direct Memory Access Controller (DMAC) IRQ 1 */
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DMAC_2_IRQn = 33, /**< 33 SAME51G18A Direct Memory Access Controller (DMAC) IRQ 2 */
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DMAC_3_IRQn = 34, /**< 34 SAME51G18A Direct Memory Access Controller (DMAC) IRQ 3 */
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DMAC_4_IRQn = 35, /**< 35 SAME51G18A Direct Memory Access Controller (DMAC) IRQ 4 */
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EVSYS_0_IRQn = 36, /**< 36 SAME51G18A Event System Interface (EVSYS) IRQ 0 */
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EVSYS_1_IRQn = 37, /**< 37 SAME51G18A Event System Interface (EVSYS) IRQ 1 */
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EVSYS_2_IRQn = 38, /**< 38 SAME51G18A Event System Interface (EVSYS) IRQ 2 */
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EVSYS_3_IRQn = 39, /**< 39 SAME51G18A Event System Interface (EVSYS) IRQ 3 */
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EVSYS_4_IRQn = 40, /**< 40 SAME51G18A Event System Interface (EVSYS) IRQ 4 */
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PAC_IRQn = 41, /**< 41 SAME51G18A Peripheral Access Controller (PAC) */
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RAMECC_IRQn = 45, /**< 45 SAME51G18A RAM ECC (RAMECC) */
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SERCOM0_0_IRQn = 46, /**< 46 SAME51G18A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
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SERCOM0_1_IRQn = 47, /**< 47 SAME51G18A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
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SERCOM0_2_IRQn = 48, /**< 48 SAME51G18A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
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SERCOM0_3_IRQn = 49, /**< 49 SAME51G18A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
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SERCOM1_0_IRQn = 50, /**< 50 SAME51G18A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
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SERCOM1_1_IRQn = 51, /**< 51 SAME51G18A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
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SERCOM1_2_IRQn = 52, /**< 52 SAME51G18A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
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SERCOM1_3_IRQn = 53, /**< 53 SAME51G18A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
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SERCOM2_0_IRQn = 54, /**< 54 SAME51G18A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
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SERCOM2_1_IRQn = 55, /**< 55 SAME51G18A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
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SERCOM2_2_IRQn = 56, /**< 56 SAME51G18A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
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SERCOM2_3_IRQn = 57, /**< 57 SAME51G18A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
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SERCOM3_0_IRQn = 58, /**< 58 SAME51G18A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
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SERCOM3_1_IRQn = 59, /**< 59 SAME51G18A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
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SERCOM3_2_IRQn = 60, /**< 60 SAME51G18A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
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SERCOM3_3_IRQn = 61, /**< 61 SAME51G18A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
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SERCOM4_0_IRQn = 62, /**< 62 SAME51G18A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
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SERCOM4_1_IRQn = 63, /**< 63 SAME51G18A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
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SERCOM4_2_IRQn = 64, /**< 64 SAME51G18A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
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SERCOM4_3_IRQn = 65, /**< 65 SAME51G18A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
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SERCOM5_0_IRQn = 66, /**< 66 SAME51G18A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
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SERCOM5_1_IRQn = 67, /**< 67 SAME51G18A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
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SERCOM5_2_IRQn = 68, /**< 68 SAME51G18A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
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SERCOM5_3_IRQn = 69, /**< 69 SAME51G18A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
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CAN0_IRQn = 78, /**< 78 SAME51G18A Control Area Network 0 (CAN0) */
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USB_0_IRQn = 80, /**< 80 SAME51G18A Universal Serial Bus (USB) IRQ 0 */
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USB_1_IRQn = 81, /**< 81 SAME51G18A Universal Serial Bus (USB) IRQ 1 */
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USB_2_IRQn = 82, /**< 82 SAME51G18A Universal Serial Bus (USB) IRQ 2 */
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USB_3_IRQn = 83, /**< 83 SAME51G18A Universal Serial Bus (USB) IRQ 3 */
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TCC0_0_IRQn = 85, /**< 85 SAME51G18A Timer Counter Control 0 (TCC0) IRQ 0 */
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TCC0_1_IRQn = 86, /**< 86 SAME51G18A Timer Counter Control 0 (TCC0) IRQ 1 */
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TCC0_2_IRQn = 87, /**< 87 SAME51G18A Timer Counter Control 0 (TCC0) IRQ 2 */
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TCC0_3_IRQn = 88, /**< 88 SAME51G18A Timer Counter Control 0 (TCC0) IRQ 3 */
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TCC0_4_IRQn = 89, /**< 89 SAME51G18A Timer Counter Control 0 (TCC0) IRQ 4 */
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TCC0_5_IRQn = 90, /**< 90 SAME51G18A Timer Counter Control 0 (TCC0) IRQ 5 */
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TCC0_6_IRQn = 91, /**< 91 SAME51G18A Timer Counter Control 0 (TCC0) IRQ 6 */
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TCC1_0_IRQn = 92, /**< 92 SAME51G18A Timer Counter Control 1 (TCC1) IRQ 0 */
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TCC1_1_IRQn = 93, /**< 93 SAME51G18A Timer Counter Control 1 (TCC1) IRQ 1 */
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TCC1_2_IRQn = 94, /**< 94 SAME51G18A Timer Counter Control 1 (TCC1) IRQ 2 */
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TCC1_3_IRQn = 95, /**< 95 SAME51G18A Timer Counter Control 1 (TCC1) IRQ 3 */
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TCC1_4_IRQn = 96, /**< 96 SAME51G18A Timer Counter Control 1 (TCC1) IRQ 4 */
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TCC2_0_IRQn = 97, /**< 97 SAME51G18A Timer Counter Control 2 (TCC2) IRQ 0 */
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TCC2_1_IRQn = 98, /**< 98 SAME51G18A Timer Counter Control 2 (TCC2) IRQ 1 */
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TCC2_2_IRQn = 99, /**< 99 SAME51G18A Timer Counter Control 2 (TCC2) IRQ 2 */
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TCC2_3_IRQn = 100, /**< 100 SAME51G18A Timer Counter Control 2 (TCC2) IRQ 3 */
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TC0_IRQn = 107, /**< 107 SAME51G18A Basic Timer Counter 0 (TC0) */
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TC1_IRQn = 108, /**< 108 SAME51G18A Basic Timer Counter 1 (TC1) */
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TC2_IRQn = 109, /**< 109 SAME51G18A Basic Timer Counter 2 (TC2) */
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TC3_IRQn = 110, /**< 110 SAME51G18A Basic Timer Counter 3 (TC3) */
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PDEC_0_IRQn = 115, /**< 115 SAME51G18A Quadrature Decodeur (PDEC) IRQ 0 */
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PDEC_1_IRQn = 116, /**< 116 SAME51G18A Quadrature Decodeur (PDEC) IRQ 1 */
|
||||
PDEC_2_IRQn = 117, /**< 117 SAME51G18A Quadrature Decodeur (PDEC) IRQ 2 */
|
||||
ADC0_0_IRQn = 118, /**< 118 SAME51G18A Analog Digital Converter 0 (ADC0) IRQ 0 */
|
||||
ADC0_1_IRQn = 119, /**< 119 SAME51G18A Analog Digital Converter 0 (ADC0) IRQ 1 */
|
||||
ADC1_0_IRQn = 120, /**< 120 SAME51G18A Analog Digital Converter 1 (ADC1) IRQ 0 */
|
||||
ADC1_1_IRQn = 121, /**< 121 SAME51G18A Analog Digital Converter 1 (ADC1) IRQ 1 */
|
||||
AC_IRQn = 122, /**< 122 SAME51G18A Analog Comparators (AC) */
|
||||
DAC_0_IRQn = 123, /**< 123 SAME51G18A Digital-to-Analog Converter (DAC) IRQ 0 */
|
||||
DAC_1_IRQn = 124, /**< 124 SAME51G18A Digital-to-Analog Converter (DAC) IRQ 1 */
|
||||
DAC_2_IRQn = 125, /**< 125 SAME51G18A Digital-to-Analog Converter (DAC) IRQ 2 */
|
||||
DAC_3_IRQn = 126, /**< 126 SAME51G18A Digital-to-Analog Converter (DAC) IRQ 3 */
|
||||
DAC_4_IRQn = 127, /**< 127 SAME51G18A Digital-to-Analog Converter (DAC) IRQ 4 */
|
||||
PCC_IRQn = 129, /**< 129 SAME51G18A Parallel Capture Controller (PCC) */
|
||||
AES_IRQn = 130, /**< 130 SAME51G18A Advanced Encryption Standard (AES) */
|
||||
TRNG_IRQn = 131, /**< 131 SAME51G18A True Random Generator (TRNG) */
|
||||
ICM_IRQn = 132, /**< 132 SAME51G18A Integrity Check Monitor (ICM) */
|
||||
PUKCC_IRQn = 133, /**< 133 SAME51G18A PUblic-Key Cryptography Controller (PUKCC) */
|
||||
QSPI_IRQn = 134, /**< 134 SAME51G18A Quad SPI interface (QSPI) */
|
||||
SDHC0_IRQn = 135, /**< 135 SAME51G18A SD/MMC Host Controller 0 (SDHC0) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNonMaskableInt_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnMemManagement_Handler;
|
||||
void* pfnBusFault_Handler;
|
||||
void* pfnUsageFault_Handler;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVCall_Handler;
|
||||
void* pfnDebugMonitor_Handler;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnMCLK_Handler; /* 1 Main Clock */
|
||||
void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
|
||||
void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
|
||||
void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
|
||||
void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
|
||||
void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
|
||||
void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
|
||||
void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
|
||||
void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
|
||||
void* pfnWDT_Handler; /* 10 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 11 Real-Time Counter */
|
||||
void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
|
||||
void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
|
||||
void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
|
||||
void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
|
||||
void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
|
||||
void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
|
||||
void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
|
||||
void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
|
||||
void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
|
||||
void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
|
||||
void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
|
||||
void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
|
||||
void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
|
||||
void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
|
||||
void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
|
||||
void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
|
||||
void* pfnFREQM_Handler; /* 28 Frequency Meter */
|
||||
void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
|
||||
void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
|
||||
void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
|
||||
void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
|
||||
void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
|
||||
void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
|
||||
void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
|
||||
void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
|
||||
void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
|
||||
void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
|
||||
void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
|
||||
void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
|
||||
void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
|
||||
void* pvReserved42;
|
||||
void* pvReserved43;
|
||||
void* pvReserved44;
|
||||
void* pfnRAMECC_Handler; /* 45 RAM ECC */
|
||||
void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
|
||||
void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
|
||||
void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
|
||||
void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
|
||||
void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
|
||||
void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
|
||||
void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
|
||||
void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
|
||||
void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
|
||||
void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
|
||||
void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
|
||||
void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
|
||||
void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
|
||||
void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
|
||||
void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
|
||||
void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
|
||||
void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
|
||||
void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
|
||||
void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
|
||||
void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
|
||||
void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
|
||||
void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
|
||||
void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
|
||||
void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
|
||||
void* pvReserved70;
|
||||
void* pvReserved71;
|
||||
void* pvReserved72;
|
||||
void* pvReserved73;
|
||||
void* pvReserved74;
|
||||
void* pvReserved75;
|
||||
void* pvReserved76;
|
||||
void* pvReserved77;
|
||||
void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
|
||||
void* pvReserved79;
|
||||
void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
|
||||
void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
|
||||
void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
|
||||
void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
|
||||
void* pvReserved84;
|
||||
void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
|
||||
void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
|
||||
void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
|
||||
void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
|
||||
void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
|
||||
void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
|
||||
void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
|
||||
void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
|
||||
void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
|
||||
void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
|
||||
void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
|
||||
void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
|
||||
void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
|
||||
void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
|
||||
void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
|
||||
void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
|
||||
void* pvReserved101;
|
||||
void* pvReserved102;
|
||||
void* pvReserved103;
|
||||
void* pvReserved104;
|
||||
void* pvReserved105;
|
||||
void* pvReserved106;
|
||||
void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
|
||||
void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
|
||||
void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
|
||||
void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
|
||||
void* pvReserved111;
|
||||
void* pvReserved112;
|
||||
void* pvReserved113;
|
||||
void* pvReserved114;
|
||||
void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
|
||||
void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
|
||||
void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
|
||||
void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
|
||||
void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
|
||||
void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
|
||||
void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
|
||||
void* pfnAC_Handler; /* 122 Analog Comparators */
|
||||
void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
|
||||
void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
|
||||
void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
|
||||
void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
|
||||
void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
|
||||
void* pvReserved128;
|
||||
void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
|
||||
void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
|
||||
void* pfnTRNG_Handler; /* 131 True Random Generator */
|
||||
void* pfnICM_Handler; /* 132 Integrity Check Monitor */
|
||||
void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
|
||||
void* pfnQSPI_Handler; /* 134 Quad SPI interface */
|
||||
void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
|
||||
void* pvReserved136;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M4 processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NonMaskableInt_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void MemManagement_Handler ( void );
|
||||
void BusFault_Handler ( void );
|
||||
void UsageFault_Handler ( void );
|
||||
void SVCall_Handler ( void );
|
||||
void DebugMonitor_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void MCLK_Handler ( void );
|
||||
void OSCCTRL_0_Handler ( void );
|
||||
void OSCCTRL_1_Handler ( void );
|
||||
void OSCCTRL_2_Handler ( void );
|
||||
void OSCCTRL_3_Handler ( void );
|
||||
void OSCCTRL_4_Handler ( void );
|
||||
void OSC32KCTRL_Handler ( void );
|
||||
void SUPC_0_Handler ( void );
|
||||
void SUPC_1_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_0_Handler ( void );
|
||||
void EIC_1_Handler ( void );
|
||||
void EIC_2_Handler ( void );
|
||||
void EIC_3_Handler ( void );
|
||||
void EIC_4_Handler ( void );
|
||||
void EIC_5_Handler ( void );
|
||||
void EIC_6_Handler ( void );
|
||||
void EIC_7_Handler ( void );
|
||||
void EIC_8_Handler ( void );
|
||||
void EIC_9_Handler ( void );
|
||||
void EIC_10_Handler ( void );
|
||||
void EIC_11_Handler ( void );
|
||||
void EIC_12_Handler ( void );
|
||||
void EIC_13_Handler ( void );
|
||||
void EIC_14_Handler ( void );
|
||||
void EIC_15_Handler ( void );
|
||||
void FREQM_Handler ( void );
|
||||
void NVMCTRL_0_Handler ( void );
|
||||
void NVMCTRL_1_Handler ( void );
|
||||
void DMAC_0_Handler ( void );
|
||||
void DMAC_1_Handler ( void );
|
||||
void DMAC_2_Handler ( void );
|
||||
void DMAC_3_Handler ( void );
|
||||
void DMAC_4_Handler ( void );
|
||||
void EVSYS_0_Handler ( void );
|
||||
void EVSYS_1_Handler ( void );
|
||||
void EVSYS_2_Handler ( void );
|
||||
void EVSYS_3_Handler ( void );
|
||||
void EVSYS_4_Handler ( void );
|
||||
void PAC_Handler ( void );
|
||||
void RAMECC_Handler ( void );
|
||||
void SERCOM0_0_Handler ( void );
|
||||
void SERCOM0_1_Handler ( void );
|
||||
void SERCOM0_2_Handler ( void );
|
||||
void SERCOM0_3_Handler ( void );
|
||||
void SERCOM1_0_Handler ( void );
|
||||
void SERCOM1_1_Handler ( void );
|
||||
void SERCOM1_2_Handler ( void );
|
||||
void SERCOM1_3_Handler ( void );
|
||||
void SERCOM2_0_Handler ( void );
|
||||
void SERCOM2_1_Handler ( void );
|
||||
void SERCOM2_2_Handler ( void );
|
||||
void SERCOM2_3_Handler ( void );
|
||||
void SERCOM3_0_Handler ( void );
|
||||
void SERCOM3_1_Handler ( void );
|
||||
void SERCOM3_2_Handler ( void );
|
||||
void SERCOM3_3_Handler ( void );
|
||||
void SERCOM4_0_Handler ( void );
|
||||
void SERCOM4_1_Handler ( void );
|
||||
void SERCOM4_2_Handler ( void );
|
||||
void SERCOM4_3_Handler ( void );
|
||||
void SERCOM5_0_Handler ( void );
|
||||
void SERCOM5_1_Handler ( void );
|
||||
void SERCOM5_2_Handler ( void );
|
||||
void SERCOM5_3_Handler ( void );
|
||||
void CAN0_Handler ( void );
|
||||
void USB_0_Handler ( void );
|
||||
void USB_1_Handler ( void );
|
||||
void USB_2_Handler ( void );
|
||||
void USB_3_Handler ( void );
|
||||
void TCC0_0_Handler ( void );
|
||||
void TCC0_1_Handler ( void );
|
||||
void TCC0_2_Handler ( void );
|
||||
void TCC0_3_Handler ( void );
|
||||
void TCC0_4_Handler ( void );
|
||||
void TCC0_5_Handler ( void );
|
||||
void TCC0_6_Handler ( void );
|
||||
void TCC1_0_Handler ( void );
|
||||
void TCC1_1_Handler ( void );
|
||||
void TCC1_2_Handler ( void );
|
||||
void TCC1_3_Handler ( void );
|
||||
void TCC1_4_Handler ( void );
|
||||
void TCC2_0_Handler ( void );
|
||||
void TCC2_1_Handler ( void );
|
||||
void TCC2_2_Handler ( void );
|
||||
void TCC2_3_Handler ( void );
|
||||
void TC0_Handler ( void );
|
||||
void TC1_Handler ( void );
|
||||
void TC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void PDEC_0_Handler ( void );
|
||||
void PDEC_1_Handler ( void );
|
||||
void PDEC_2_Handler ( void );
|
||||
void ADC0_0_Handler ( void );
|
||||
void ADC0_1_Handler ( void );
|
||||
void ADC1_0_Handler ( void );
|
||||
void ADC1_1_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_0_Handler ( void );
|
||||
void DAC_1_Handler ( void );
|
||||
void DAC_2_Handler ( void );
|
||||
void DAC_3_Handler ( void );
|
||||
void DAC_4_Handler ( void );
|
||||
void PCC_Handler ( void );
|
||||
void AES_Handler ( void );
|
||||
void TRNG_Handler ( void );
|
||||
void ICM_Handler ( void );
|
||||
void PUKCC_Handler ( void );
|
||||
void QSPI_Handler ( void );
|
||||
void SDHC0_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __CM4_REV 1 /*!< Core revision r0p1 */
|
||||
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
|
||||
#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm4.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_same51.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME51G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G18A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/aes.h"
|
||||
#include "component/can.h"
|
||||
#include "component/ccl.h"
|
||||
#include "component/cmcc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/freqm.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/hmatrixb.h"
|
||||
#include "component/icm.h"
|
||||
#include "component/mclk.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/oscctrl.h"
|
||||
#include "component/osc32kctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pcc.h"
|
||||
#include "component/pdec.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/qspi.h"
|
||||
#include "component/ramecc.h"
|
||||
#include "component/rstc.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sdhc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/supc.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/trng.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAME51G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G18A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc0.h"
|
||||
#include "instance/adc1.h"
|
||||
#include "instance/aes.h"
|
||||
#include "instance/can0.h"
|
||||
#include "instance/ccl.h"
|
||||
#include "instance/cmcc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/freqm.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/hmatrix.h"
|
||||
#include "instance/icm.h"
|
||||
#include "instance/mclk.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/oscctrl.h"
|
||||
#include "instance/osc32kctrl.h"
|
||||
#include "instance/pac.h"
|
||||
#include "instance/pcc.h"
|
||||
#include "instance/pdec.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/pukcc.h"
|
||||
#include "instance/qspi.h"
|
||||
#include "instance/ramecc.h"
|
||||
#include "instance/rstc.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sdhc0.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/supc.h"
|
||||
#include "instance/tc0.h"
|
||||
#include "instance/tc1.h"
|
||||
#include "instance/tc2.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/trng.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAME51G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G18A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
|
||||
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
|
||||
#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
|
||||
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
|
||||
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
|
||||
#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
|
||||
#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
|
||||
#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
|
||||
#define ID_PORT 36 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
|
||||
#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
|
||||
#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
|
||||
#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
|
||||
#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
|
||||
#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
|
||||
#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
|
||||
#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */
|
||||
#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
|
||||
#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
|
||||
#define ID_AC 72 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
|
||||
#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
|
||||
#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
|
||||
#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
|
||||
#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
|
||||
#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
|
||||
|
||||
// Peripheral instances on HPB3 bridge
|
||||
#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
|
||||
#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
|
||||
#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
|
||||
#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
|
||||
#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
|
||||
#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
|
||||
|
||||
// Peripheral instances on AHB (as if on bridge 4)
|
||||
#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
|
||||
|
||||
#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAME51G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G18A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42002000) /**< \brief (AC) APB Base Address */
|
||||
#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
|
||||
#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
|
||||
#define AES (0x42002400) /**< \brief (AES) APB Base Address */
|
||||
#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */
|
||||
#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
|
||||
#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
|
||||
#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
|
||||
#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
|
||||
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
|
||||
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
|
||||
#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
|
||||
#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
|
||||
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
|
||||
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
|
||||
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
|
||||
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
|
||||
#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
|
||||
#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
|
||||
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
|
||||
#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
|
||||
#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
|
||||
#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
|
||||
#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
|
||||
#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
|
||||
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
|
||||
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
|
||||
#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
|
||||
#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
|
||||
#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
|
||||
#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
|
||||
#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
|
||||
#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
|
||||
#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
|
||||
#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
|
||||
#define USB (0x41000000) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
|
||||
#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
|
||||
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
|
||||
#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
|
||||
#define AES_INSTS { AES } /**< \brief (AES) Instances List */
|
||||
|
||||
#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */
|
||||
#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */
|
||||
#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */
|
||||
|
||||
#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
|
||||
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
|
||||
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
|
||||
|
||||
#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
|
||||
#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
|
||||
#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
|
||||
#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
|
||||
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
|
||||
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
|
||||
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
|
||||
#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
|
||||
|
||||
#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
|
||||
#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
|
||||
#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
|
||||
|
||||
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
|
||||
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
|
||||
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
|
||||
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
|
||||
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
|
||||
|
||||
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
|
||||
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
|
||||
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
|
||||
|
||||
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
|
||||
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
|
||||
#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
|
||||
#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
|
||||
|
||||
#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
|
||||
#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
|
||||
#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
|
||||
#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
|
||||
#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
|
||||
#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
|
||||
|
||||
#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
|
||||
#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
|
||||
#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
|
||||
#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
|
||||
|
||||
#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
|
||||
#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
|
||||
#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
|
||||
|
||||
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
|
||||
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
|
||||
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
|
||||
#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */
|
||||
#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
|
||||
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
|
||||
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
|
||||
|
||||
#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
|
||||
#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
|
||||
#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
|
||||
#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
|
||||
#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
|
||||
#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
|
||||
#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAME51G18A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G18A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/same51g18a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAME51G18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */
|
||||
#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */
|
||||
#define FLASH_PAGE_SIZE 512
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 512
|
||||
#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
|
||||
#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
|
||||
|
||||
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
|
||||
#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
|
||||
#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
|
||||
#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
|
||||
#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
|
||||
#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
|
||||
#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
|
||||
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
|
||||
#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
|
||||
#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
|
||||
#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
|
||||
#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
|
||||
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
|
||||
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
|
||||
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
|
||||
#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
|
||||
#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
|
||||
#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
|
||||
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE _UL_(0x61810306)
|
||||
#define ADC0_TOUCH_LINES_NUM 22
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAME51G18A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAME51G18A_H */
|
||||
|
|
@ -0,0 +1,985 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Header file for SAME51G19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAME51G19A_
|
||||
#define _SAME51G19A_
|
||||
|
||||
/**
|
||||
* \ingroup SAME51_definitions
|
||||
* \addtogroup SAME51G19A_definitions SAME51G19A definitions
|
||||
* This file defines all structures and symbols for SAME51G19A:
|
||||
* - registers and bitfields
|
||||
* - peripheral base address
|
||||
* - peripheral ID
|
||||
* - PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
|
||||
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
#endif
|
||||
|
||||
#if !defined(SKIP_INTEGER_LITERALS)
|
||||
#if defined(_U_) || defined(_L_) || defined(_UL_)
|
||||
#error "Integer Literals macros already defined elsewhere"
|
||||
#endif
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
|
||||
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
|
||||
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
|
||||
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
|
||||
#else /* Assembler */
|
||||
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
|
||||
#define _L_(x) x /**< Assembler: Long integer literal constant value */
|
||||
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* SKIP_INTEGER_LITERALS */
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** CMSIS DEFINITIONS FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G19A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers *******************/
|
||||
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
|
||||
/****** SAME51G19A-specific Interrupt Numbers *********************/
|
||||
PM_IRQn = 0, /**< 0 SAME51G19A Power Manager (PM) */
|
||||
MCLK_IRQn = 1, /**< 1 SAME51G19A Main Clock (MCLK) */
|
||||
OSCCTRL_0_IRQn = 2, /**< 2 SAME51G19A Oscillators Control (OSCCTRL) IRQ 0 */
|
||||
OSCCTRL_1_IRQn = 3, /**< 3 SAME51G19A Oscillators Control (OSCCTRL) IRQ 1 */
|
||||
OSCCTRL_2_IRQn = 4, /**< 4 SAME51G19A Oscillators Control (OSCCTRL) IRQ 2 */
|
||||
OSCCTRL_3_IRQn = 5, /**< 5 SAME51G19A Oscillators Control (OSCCTRL) IRQ 3 */
|
||||
OSCCTRL_4_IRQn = 6, /**< 6 SAME51G19A Oscillators Control (OSCCTRL) IRQ 4 */
|
||||
OSC32KCTRL_IRQn = 7, /**< 7 SAME51G19A 32kHz Oscillators Control (OSC32KCTRL) */
|
||||
SUPC_0_IRQn = 8, /**< 8 SAME51G19A Supply Controller (SUPC) IRQ 0 */
|
||||
SUPC_1_IRQn = 9, /**< 9 SAME51G19A Supply Controller (SUPC) IRQ 1 */
|
||||
WDT_IRQn = 10, /**< 10 SAME51G19A Watchdog Timer (WDT) */
|
||||
RTC_IRQn = 11, /**< 11 SAME51G19A Real-Time Counter (RTC) */
|
||||
EIC_0_IRQn = 12, /**< 12 SAME51G19A External Interrupt Controller (EIC) IRQ 0 */
|
||||
EIC_1_IRQn = 13, /**< 13 SAME51G19A External Interrupt Controller (EIC) IRQ 1 */
|
||||
EIC_2_IRQn = 14, /**< 14 SAME51G19A External Interrupt Controller (EIC) IRQ 2 */
|
||||
EIC_3_IRQn = 15, /**< 15 SAME51G19A External Interrupt Controller (EIC) IRQ 3 */
|
||||
EIC_4_IRQn = 16, /**< 16 SAME51G19A External Interrupt Controller (EIC) IRQ 4 */
|
||||
EIC_5_IRQn = 17, /**< 17 SAME51G19A External Interrupt Controller (EIC) IRQ 5 */
|
||||
EIC_6_IRQn = 18, /**< 18 SAME51G19A External Interrupt Controller (EIC) IRQ 6 */
|
||||
EIC_7_IRQn = 19, /**< 19 SAME51G19A External Interrupt Controller (EIC) IRQ 7 */
|
||||
EIC_8_IRQn = 20, /**< 20 SAME51G19A External Interrupt Controller (EIC) IRQ 8 */
|
||||
EIC_9_IRQn = 21, /**< 21 SAME51G19A External Interrupt Controller (EIC) IRQ 9 */
|
||||
EIC_10_IRQn = 22, /**< 22 SAME51G19A External Interrupt Controller (EIC) IRQ 10 */
|
||||
EIC_11_IRQn = 23, /**< 23 SAME51G19A External Interrupt Controller (EIC) IRQ 11 */
|
||||
EIC_12_IRQn = 24, /**< 24 SAME51G19A External Interrupt Controller (EIC) IRQ 12 */
|
||||
EIC_13_IRQn = 25, /**< 25 SAME51G19A External Interrupt Controller (EIC) IRQ 13 */
|
||||
EIC_14_IRQn = 26, /**< 26 SAME51G19A External Interrupt Controller (EIC) IRQ 14 */
|
||||
EIC_15_IRQn = 27, /**< 27 SAME51G19A External Interrupt Controller (EIC) IRQ 15 */
|
||||
FREQM_IRQn = 28, /**< 28 SAME51G19A Frequency Meter (FREQM) */
|
||||
NVMCTRL_0_IRQn = 29, /**< 29 SAME51G19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
|
||||
NVMCTRL_1_IRQn = 30, /**< 30 SAME51G19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
|
||||
DMAC_0_IRQn = 31, /**< 31 SAME51G19A Direct Memory Access Controller (DMAC) IRQ 0 */
|
||||
DMAC_1_IRQn = 32, /**< 32 SAME51G19A Direct Memory Access Controller (DMAC) IRQ 1 */
|
||||
DMAC_2_IRQn = 33, /**< 33 SAME51G19A Direct Memory Access Controller (DMAC) IRQ 2 */
|
||||
DMAC_3_IRQn = 34, /**< 34 SAME51G19A Direct Memory Access Controller (DMAC) IRQ 3 */
|
||||
DMAC_4_IRQn = 35, /**< 35 SAME51G19A Direct Memory Access Controller (DMAC) IRQ 4 */
|
||||
EVSYS_0_IRQn = 36, /**< 36 SAME51G19A Event System Interface (EVSYS) IRQ 0 */
|
||||
EVSYS_1_IRQn = 37, /**< 37 SAME51G19A Event System Interface (EVSYS) IRQ 1 */
|
||||
EVSYS_2_IRQn = 38, /**< 38 SAME51G19A Event System Interface (EVSYS) IRQ 2 */
|
||||
EVSYS_3_IRQn = 39, /**< 39 SAME51G19A Event System Interface (EVSYS) IRQ 3 */
|
||||
EVSYS_4_IRQn = 40, /**< 40 SAME51G19A Event System Interface (EVSYS) IRQ 4 */
|
||||
PAC_IRQn = 41, /**< 41 SAME51G19A Peripheral Access Controller (PAC) */
|
||||
RAMECC_IRQn = 45, /**< 45 SAME51G19A RAM ECC (RAMECC) */
|
||||
SERCOM0_0_IRQn = 46, /**< 46 SAME51G19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
|
||||
SERCOM0_1_IRQn = 47, /**< 47 SAME51G19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
|
||||
SERCOM0_2_IRQn = 48, /**< 48 SAME51G19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
|
||||
SERCOM0_3_IRQn = 49, /**< 49 SAME51G19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
|
||||
SERCOM1_0_IRQn = 50, /**< 50 SAME51G19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
|
||||
SERCOM1_1_IRQn = 51, /**< 51 SAME51G19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
|
||||
SERCOM1_2_IRQn = 52, /**< 52 SAME51G19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
|
||||
SERCOM1_3_IRQn = 53, /**< 53 SAME51G19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
|
||||
SERCOM2_0_IRQn = 54, /**< 54 SAME51G19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
|
||||
SERCOM2_1_IRQn = 55, /**< 55 SAME51G19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
|
||||
SERCOM2_2_IRQn = 56, /**< 56 SAME51G19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
|
||||
SERCOM2_3_IRQn = 57, /**< 57 SAME51G19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
|
||||
SERCOM3_0_IRQn = 58, /**< 58 SAME51G19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
|
||||
SERCOM3_1_IRQn = 59, /**< 59 SAME51G19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
|
||||
SERCOM3_2_IRQn = 60, /**< 60 SAME51G19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
|
||||
SERCOM3_3_IRQn = 61, /**< 61 SAME51G19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
|
||||
SERCOM4_0_IRQn = 62, /**< 62 SAME51G19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
|
||||
SERCOM4_1_IRQn = 63, /**< 63 SAME51G19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
|
||||
SERCOM4_2_IRQn = 64, /**< 64 SAME51G19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
|
||||
SERCOM4_3_IRQn = 65, /**< 65 SAME51G19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
|
||||
SERCOM5_0_IRQn = 66, /**< 66 SAME51G19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
|
||||
SERCOM5_1_IRQn = 67, /**< 67 SAME51G19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
|
||||
SERCOM5_2_IRQn = 68, /**< 68 SAME51G19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
|
||||
SERCOM5_3_IRQn = 69, /**< 69 SAME51G19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
|
||||
CAN0_IRQn = 78, /**< 78 SAME51G19A Control Area Network 0 (CAN0) */
|
||||
USB_0_IRQn = 80, /**< 80 SAME51G19A Universal Serial Bus (USB) IRQ 0 */
|
||||
USB_1_IRQn = 81, /**< 81 SAME51G19A Universal Serial Bus (USB) IRQ 1 */
|
||||
USB_2_IRQn = 82, /**< 82 SAME51G19A Universal Serial Bus (USB) IRQ 2 */
|
||||
USB_3_IRQn = 83, /**< 83 SAME51G19A Universal Serial Bus (USB) IRQ 3 */
|
||||
TCC0_0_IRQn = 85, /**< 85 SAME51G19A Timer Counter Control 0 (TCC0) IRQ 0 */
|
||||
TCC0_1_IRQn = 86, /**< 86 SAME51G19A Timer Counter Control 0 (TCC0) IRQ 1 */
|
||||
TCC0_2_IRQn = 87, /**< 87 SAME51G19A Timer Counter Control 0 (TCC0) IRQ 2 */
|
||||
TCC0_3_IRQn = 88, /**< 88 SAME51G19A Timer Counter Control 0 (TCC0) IRQ 3 */
|
||||
TCC0_4_IRQn = 89, /**< 89 SAME51G19A Timer Counter Control 0 (TCC0) IRQ 4 */
|
||||
TCC0_5_IRQn = 90, /**< 90 SAME51G19A Timer Counter Control 0 (TCC0) IRQ 5 */
|
||||
TCC0_6_IRQn = 91, /**< 91 SAME51G19A Timer Counter Control 0 (TCC0) IRQ 6 */
|
||||
TCC1_0_IRQn = 92, /**< 92 SAME51G19A Timer Counter Control 1 (TCC1) IRQ 0 */
|
||||
TCC1_1_IRQn = 93, /**< 93 SAME51G19A Timer Counter Control 1 (TCC1) IRQ 1 */
|
||||
TCC1_2_IRQn = 94, /**< 94 SAME51G19A Timer Counter Control 1 (TCC1) IRQ 2 */
|
||||
TCC1_3_IRQn = 95, /**< 95 SAME51G19A Timer Counter Control 1 (TCC1) IRQ 3 */
|
||||
TCC1_4_IRQn = 96, /**< 96 SAME51G19A Timer Counter Control 1 (TCC1) IRQ 4 */
|
||||
TCC2_0_IRQn = 97, /**< 97 SAME51G19A Timer Counter Control 2 (TCC2) IRQ 0 */
|
||||
TCC2_1_IRQn = 98, /**< 98 SAME51G19A Timer Counter Control 2 (TCC2) IRQ 1 */
|
||||
TCC2_2_IRQn = 99, /**< 99 SAME51G19A Timer Counter Control 2 (TCC2) IRQ 2 */
|
||||
TCC2_3_IRQn = 100, /**< 100 SAME51G19A Timer Counter Control 2 (TCC2) IRQ 3 */
|
||||
TC0_IRQn = 107, /**< 107 SAME51G19A Basic Timer Counter 0 (TC0) */
|
||||
TC1_IRQn = 108, /**< 108 SAME51G19A Basic Timer Counter 1 (TC1) */
|
||||
TC2_IRQn = 109, /**< 109 SAME51G19A Basic Timer Counter 2 (TC2) */
|
||||
TC3_IRQn = 110, /**< 110 SAME51G19A Basic Timer Counter 3 (TC3) */
|
||||
PDEC_0_IRQn = 115, /**< 115 SAME51G19A Quadrature Decodeur (PDEC) IRQ 0 */
|
||||
PDEC_1_IRQn = 116, /**< 116 SAME51G19A Quadrature Decodeur (PDEC) IRQ 1 */
|
||||
PDEC_2_IRQn = 117, /**< 117 SAME51G19A Quadrature Decodeur (PDEC) IRQ 2 */
|
||||
ADC0_0_IRQn = 118, /**< 118 SAME51G19A Analog Digital Converter 0 (ADC0) IRQ 0 */
|
||||
ADC0_1_IRQn = 119, /**< 119 SAME51G19A Analog Digital Converter 0 (ADC0) IRQ 1 */
|
||||
ADC1_0_IRQn = 120, /**< 120 SAME51G19A Analog Digital Converter 1 (ADC1) IRQ 0 */
|
||||
ADC1_1_IRQn = 121, /**< 121 SAME51G19A Analog Digital Converter 1 (ADC1) IRQ 1 */
|
||||
AC_IRQn = 122, /**< 122 SAME51G19A Analog Comparators (AC) */
|
||||
DAC_0_IRQn = 123, /**< 123 SAME51G19A Digital-to-Analog Converter (DAC) IRQ 0 */
|
||||
DAC_1_IRQn = 124, /**< 124 SAME51G19A Digital-to-Analog Converter (DAC) IRQ 1 */
|
||||
DAC_2_IRQn = 125, /**< 125 SAME51G19A Digital-to-Analog Converter (DAC) IRQ 2 */
|
||||
DAC_3_IRQn = 126, /**< 126 SAME51G19A Digital-to-Analog Converter (DAC) IRQ 3 */
|
||||
DAC_4_IRQn = 127, /**< 127 SAME51G19A Digital-to-Analog Converter (DAC) IRQ 4 */
|
||||
PCC_IRQn = 129, /**< 129 SAME51G19A Parallel Capture Controller (PCC) */
|
||||
AES_IRQn = 130, /**< 130 SAME51G19A Advanced Encryption Standard (AES) */
|
||||
TRNG_IRQn = 131, /**< 131 SAME51G19A True Random Generator (TRNG) */
|
||||
ICM_IRQn = 132, /**< 132 SAME51G19A Integrity Check Monitor (ICM) */
|
||||
PUKCC_IRQn = 133, /**< 133 SAME51G19A PUblic-Key Cryptography Controller (PUKCC) */
|
||||
QSPI_IRQn = 134, /**< 134 SAME51G19A Quad SPI interface (QSPI) */
|
||||
SDHC0_IRQn = 135, /**< 135 SAME51G19A SD/MMC Host Controller 0 (SDHC0) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
{
|
||||
/* Stack pointer */
|
||||
void* pvStack;
|
||||
|
||||
/* Cortex-M handlers */
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNonMaskableInt_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnMemManagement_Handler;
|
||||
void* pfnBusFault_Handler;
|
||||
void* pfnUsageFault_Handler;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVCall_Handler;
|
||||
void* pfnDebugMonitor_Handler;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
/* Peripheral handlers */
|
||||
void* pfnPM_Handler; /* 0 Power Manager */
|
||||
void* pfnMCLK_Handler; /* 1 Main Clock */
|
||||
void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
|
||||
void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
|
||||
void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
|
||||
void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
|
||||
void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
|
||||
void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
|
||||
void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
|
||||
void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
|
||||
void* pfnWDT_Handler; /* 10 Watchdog Timer */
|
||||
void* pfnRTC_Handler; /* 11 Real-Time Counter */
|
||||
void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
|
||||
void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
|
||||
void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
|
||||
void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
|
||||
void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
|
||||
void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
|
||||
void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
|
||||
void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
|
||||
void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
|
||||
void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
|
||||
void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
|
||||
void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
|
||||
void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
|
||||
void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
|
||||
void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
|
||||
void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
|
||||
void* pfnFREQM_Handler; /* 28 Frequency Meter */
|
||||
void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
|
||||
void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
|
||||
void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
|
||||
void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
|
||||
void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
|
||||
void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
|
||||
void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
|
||||
void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
|
||||
void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
|
||||
void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
|
||||
void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
|
||||
void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
|
||||
void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
|
||||
void* pvReserved42;
|
||||
void* pvReserved43;
|
||||
void* pvReserved44;
|
||||
void* pfnRAMECC_Handler; /* 45 RAM ECC */
|
||||
void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
|
||||
void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
|
||||
void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
|
||||
void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
|
||||
void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
|
||||
void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
|
||||
void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
|
||||
void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
|
||||
void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
|
||||
void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
|
||||
void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
|
||||
void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
|
||||
void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
|
||||
void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
|
||||
void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
|
||||
void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
|
||||
void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
|
||||
void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
|
||||
void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
|
||||
void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
|
||||
void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
|
||||
void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
|
||||
void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
|
||||
void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
|
||||
void* pvReserved70;
|
||||
void* pvReserved71;
|
||||
void* pvReserved72;
|
||||
void* pvReserved73;
|
||||
void* pvReserved74;
|
||||
void* pvReserved75;
|
||||
void* pvReserved76;
|
||||
void* pvReserved77;
|
||||
void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
|
||||
void* pvReserved79;
|
||||
void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
|
||||
void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
|
||||
void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
|
||||
void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
|
||||
void* pvReserved84;
|
||||
void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
|
||||
void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
|
||||
void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
|
||||
void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
|
||||
void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
|
||||
void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
|
||||
void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
|
||||
void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
|
||||
void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
|
||||
void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
|
||||
void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
|
||||
void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
|
||||
void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
|
||||
void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
|
||||
void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
|
||||
void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
|
||||
void* pvReserved101;
|
||||
void* pvReserved102;
|
||||
void* pvReserved103;
|
||||
void* pvReserved104;
|
||||
void* pvReserved105;
|
||||
void* pvReserved106;
|
||||
void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
|
||||
void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
|
||||
void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
|
||||
void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
|
||||
void* pvReserved111;
|
||||
void* pvReserved112;
|
||||
void* pvReserved113;
|
||||
void* pvReserved114;
|
||||
void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
|
||||
void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
|
||||
void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
|
||||
void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
|
||||
void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
|
||||
void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
|
||||
void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
|
||||
void* pfnAC_Handler; /* 122 Analog Comparators */
|
||||
void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
|
||||
void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
|
||||
void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
|
||||
void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
|
||||
void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
|
||||
void* pvReserved128;
|
||||
void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
|
||||
void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
|
||||
void* pfnTRNG_Handler; /* 131 True Random Generator */
|
||||
void* pfnICM_Handler; /* 132 Integrity Check Monitor */
|
||||
void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
|
||||
void* pfnQSPI_Handler; /* 134 Quad SPI interface */
|
||||
void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
|
||||
void* pvReserved136;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M4 processor handlers */
|
||||
void Reset_Handler ( void );
|
||||
void NonMaskableInt_Handler ( void );
|
||||
void HardFault_Handler ( void );
|
||||
void MemManagement_Handler ( void );
|
||||
void BusFault_Handler ( void );
|
||||
void UsageFault_Handler ( void );
|
||||
void SVCall_Handler ( void );
|
||||
void DebugMonitor_Handler ( void );
|
||||
void PendSV_Handler ( void );
|
||||
void SysTick_Handler ( void );
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void );
|
||||
void MCLK_Handler ( void );
|
||||
void OSCCTRL_0_Handler ( void );
|
||||
void OSCCTRL_1_Handler ( void );
|
||||
void OSCCTRL_2_Handler ( void );
|
||||
void OSCCTRL_3_Handler ( void );
|
||||
void OSCCTRL_4_Handler ( void );
|
||||
void OSC32KCTRL_Handler ( void );
|
||||
void SUPC_0_Handler ( void );
|
||||
void SUPC_1_Handler ( void );
|
||||
void WDT_Handler ( void );
|
||||
void RTC_Handler ( void );
|
||||
void EIC_0_Handler ( void );
|
||||
void EIC_1_Handler ( void );
|
||||
void EIC_2_Handler ( void );
|
||||
void EIC_3_Handler ( void );
|
||||
void EIC_4_Handler ( void );
|
||||
void EIC_5_Handler ( void );
|
||||
void EIC_6_Handler ( void );
|
||||
void EIC_7_Handler ( void );
|
||||
void EIC_8_Handler ( void );
|
||||
void EIC_9_Handler ( void );
|
||||
void EIC_10_Handler ( void );
|
||||
void EIC_11_Handler ( void );
|
||||
void EIC_12_Handler ( void );
|
||||
void EIC_13_Handler ( void );
|
||||
void EIC_14_Handler ( void );
|
||||
void EIC_15_Handler ( void );
|
||||
void FREQM_Handler ( void );
|
||||
void NVMCTRL_0_Handler ( void );
|
||||
void NVMCTRL_1_Handler ( void );
|
||||
void DMAC_0_Handler ( void );
|
||||
void DMAC_1_Handler ( void );
|
||||
void DMAC_2_Handler ( void );
|
||||
void DMAC_3_Handler ( void );
|
||||
void DMAC_4_Handler ( void );
|
||||
void EVSYS_0_Handler ( void );
|
||||
void EVSYS_1_Handler ( void );
|
||||
void EVSYS_2_Handler ( void );
|
||||
void EVSYS_3_Handler ( void );
|
||||
void EVSYS_4_Handler ( void );
|
||||
void PAC_Handler ( void );
|
||||
void RAMECC_Handler ( void );
|
||||
void SERCOM0_0_Handler ( void );
|
||||
void SERCOM0_1_Handler ( void );
|
||||
void SERCOM0_2_Handler ( void );
|
||||
void SERCOM0_3_Handler ( void );
|
||||
void SERCOM1_0_Handler ( void );
|
||||
void SERCOM1_1_Handler ( void );
|
||||
void SERCOM1_2_Handler ( void );
|
||||
void SERCOM1_3_Handler ( void );
|
||||
void SERCOM2_0_Handler ( void );
|
||||
void SERCOM2_1_Handler ( void );
|
||||
void SERCOM2_2_Handler ( void );
|
||||
void SERCOM2_3_Handler ( void );
|
||||
void SERCOM3_0_Handler ( void );
|
||||
void SERCOM3_1_Handler ( void );
|
||||
void SERCOM3_2_Handler ( void );
|
||||
void SERCOM3_3_Handler ( void );
|
||||
void SERCOM4_0_Handler ( void );
|
||||
void SERCOM4_1_Handler ( void );
|
||||
void SERCOM4_2_Handler ( void );
|
||||
void SERCOM4_3_Handler ( void );
|
||||
void SERCOM5_0_Handler ( void );
|
||||
void SERCOM5_1_Handler ( void );
|
||||
void SERCOM5_2_Handler ( void );
|
||||
void SERCOM5_3_Handler ( void );
|
||||
void CAN0_Handler ( void );
|
||||
void USB_0_Handler ( void );
|
||||
void USB_1_Handler ( void );
|
||||
void USB_2_Handler ( void );
|
||||
void USB_3_Handler ( void );
|
||||
void TCC0_0_Handler ( void );
|
||||
void TCC0_1_Handler ( void );
|
||||
void TCC0_2_Handler ( void );
|
||||
void TCC0_3_Handler ( void );
|
||||
void TCC0_4_Handler ( void );
|
||||
void TCC0_5_Handler ( void );
|
||||
void TCC0_6_Handler ( void );
|
||||
void TCC1_0_Handler ( void );
|
||||
void TCC1_1_Handler ( void );
|
||||
void TCC1_2_Handler ( void );
|
||||
void TCC1_3_Handler ( void );
|
||||
void TCC1_4_Handler ( void );
|
||||
void TCC2_0_Handler ( void );
|
||||
void TCC2_1_Handler ( void );
|
||||
void TCC2_2_Handler ( void );
|
||||
void TCC2_3_Handler ( void );
|
||||
void TC0_Handler ( void );
|
||||
void TC1_Handler ( void );
|
||||
void TC2_Handler ( void );
|
||||
void TC3_Handler ( void );
|
||||
void PDEC_0_Handler ( void );
|
||||
void PDEC_1_Handler ( void );
|
||||
void PDEC_2_Handler ( void );
|
||||
void ADC0_0_Handler ( void );
|
||||
void ADC0_1_Handler ( void );
|
||||
void ADC1_0_Handler ( void );
|
||||
void ADC1_1_Handler ( void );
|
||||
void AC_Handler ( void );
|
||||
void DAC_0_Handler ( void );
|
||||
void DAC_1_Handler ( void );
|
||||
void DAC_2_Handler ( void );
|
||||
void DAC_3_Handler ( void );
|
||||
void DAC_4_Handler ( void );
|
||||
void PCC_Handler ( void );
|
||||
void AES_Handler ( void );
|
||||
void TRNG_Handler ( void );
|
||||
void ICM_Handler ( void );
|
||||
void PUKCC_Handler ( void );
|
||||
void QSPI_Handler ( void );
|
||||
void SDHC0_Handler ( void );
|
||||
|
||||
/*
|
||||
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __CM4_REV 1 /*!< Core revision r0p1 */
|
||||
#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
|
||||
#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/**
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm4.h>
|
||||
#if !defined DONT_USE_CMSIS_INIT
|
||||
#include "system_same51.h"
|
||||
#endif /* DONT_USE_CMSIS_INIT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G19A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ac.h"
|
||||
#include "component/adc.h"
|
||||
#include "component/aes.h"
|
||||
#include "component/can.h"
|
||||
#include "component/ccl.h"
|
||||
#include "component/cmcc.h"
|
||||
#include "component/dac.h"
|
||||
#include "component/dmac.h"
|
||||
#include "component/dsu.h"
|
||||
#include "component/eic.h"
|
||||
#include "component/evsys.h"
|
||||
#include "component/freqm.h"
|
||||
#include "component/gclk.h"
|
||||
#include "component/hmatrixb.h"
|
||||
#include "component/icm.h"
|
||||
#include "component/mclk.h"
|
||||
#include "component/nvmctrl.h"
|
||||
#include "component/oscctrl.h"
|
||||
#include "component/osc32kctrl.h"
|
||||
#include "component/pac.h"
|
||||
#include "component/pcc.h"
|
||||
#include "component/pdec.h"
|
||||
#include "component/pm.h"
|
||||
#include "component/port.h"
|
||||
#include "component/qspi.h"
|
||||
#include "component/ramecc.h"
|
||||
#include "component/rstc.h"
|
||||
#include "component/rtc.h"
|
||||
#include "component/sdhc.h"
|
||||
#include "component/sercom.h"
|
||||
#include "component/supc.h"
|
||||
#include "component/tc.h"
|
||||
#include "component/tcc.h"
|
||||
#include "component/trng.h"
|
||||
#include "component/usb.h"
|
||||
#include "component/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** REGISTERS ACCESS DEFINITIONS FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G19A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/ac.h"
|
||||
#include "instance/adc0.h"
|
||||
#include "instance/adc1.h"
|
||||
#include "instance/aes.h"
|
||||
#include "instance/can0.h"
|
||||
#include "instance/ccl.h"
|
||||
#include "instance/cmcc.h"
|
||||
#include "instance/dac.h"
|
||||
#include "instance/dmac.h"
|
||||
#include "instance/dsu.h"
|
||||
#include "instance/eic.h"
|
||||
#include "instance/evsys.h"
|
||||
#include "instance/freqm.h"
|
||||
#include "instance/gclk.h"
|
||||
#include "instance/hmatrix.h"
|
||||
#include "instance/icm.h"
|
||||
#include "instance/mclk.h"
|
||||
#include "instance/nvmctrl.h"
|
||||
#include "instance/oscctrl.h"
|
||||
#include "instance/osc32kctrl.h"
|
||||
#include "instance/pac.h"
|
||||
#include "instance/pcc.h"
|
||||
#include "instance/pdec.h"
|
||||
#include "instance/pm.h"
|
||||
#include "instance/port.h"
|
||||
#include "instance/pukcc.h"
|
||||
#include "instance/qspi.h"
|
||||
#include "instance/ramecc.h"
|
||||
#include "instance/rstc.h"
|
||||
#include "instance/rtc.h"
|
||||
#include "instance/sdhc0.h"
|
||||
#include "instance/sercom0.h"
|
||||
#include "instance/sercom1.h"
|
||||
#include "instance/sercom2.h"
|
||||
#include "instance/sercom3.h"
|
||||
#include "instance/sercom4.h"
|
||||
#include "instance/sercom5.h"
|
||||
#include "instance/supc.h"
|
||||
#include "instance/tc0.h"
|
||||
#include "instance/tc1.h"
|
||||
#include "instance/tc2.h"
|
||||
#include "instance/tc3.h"
|
||||
#include "instance/tcc0.h"
|
||||
#include "instance/tcc1.h"
|
||||
#include "instance/tcc2.h"
|
||||
#include "instance/trng.h"
|
||||
#include "instance/usb.h"
|
||||
#include "instance/wdt.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PERIPHERAL ID DEFINITIONS FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G19A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
// Peripheral instances on HPB0 bridge
|
||||
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
|
||||
#define ID_PM 1 /**< \brief Power Manager (PM) */
|
||||
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
|
||||
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
|
||||
#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
|
||||
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
|
||||
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
|
||||
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
|
||||
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
|
||||
#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
|
||||
#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
|
||||
#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
|
||||
|
||||
// Peripheral instances on HPB1 bridge
|
||||
#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
|
||||
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
|
||||
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
|
||||
#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
|
||||
#define ID_PORT 36 /**< \brief Port Module (PORT) */
|
||||
#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
|
||||
#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
|
||||
#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
|
||||
#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
|
||||
#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
|
||||
#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
|
||||
#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
|
||||
#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
|
||||
#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
|
||||
#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
|
||||
|
||||
// Peripheral instances on HPB2 bridge
|
||||
#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */
|
||||
#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
|
||||
#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
|
||||
#define ID_AC 72 /**< \brief Analog Comparators (AC) */
|
||||
#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
|
||||
#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
|
||||
#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
|
||||
#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
|
||||
#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
|
||||
#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
|
||||
|
||||
// Peripheral instances on HPB3 bridge
|
||||
#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
|
||||
#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
|
||||
#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
|
||||
#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
|
||||
#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
|
||||
#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
|
||||
|
||||
// Peripheral instances on AHB (as if on bridge 4)
|
||||
#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
|
||||
|
||||
#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** BASE ADDRESS DEFINITIONS FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G19A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
|
||||
#define AC (0x42002000) /**< \brief (AC) APB Base Address */
|
||||
#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
|
||||
#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
|
||||
#define AES (0x42002400) /**< \brief (AES) APB Base Address */
|
||||
#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */
|
||||
#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
|
||||
#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
|
||||
#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
|
||||
#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
|
||||
#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
|
||||
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
|
||||
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
|
||||
#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
|
||||
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
|
||||
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
|
||||
#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
|
||||
#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
|
||||
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
|
||||
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
|
||||
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
|
||||
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
|
||||
#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
|
||||
#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
|
||||
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
|
||||
#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
|
||||
#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
|
||||
#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
|
||||
#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
|
||||
#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
|
||||
#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
|
||||
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
|
||||
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
|
||||
#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
|
||||
#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
|
||||
#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
|
||||
#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
|
||||
#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
|
||||
#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
|
||||
#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
|
||||
#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
|
||||
#define USB (0x41000000) /**< \brief (USB) APB Base Address */
|
||||
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
|
||||
#else
|
||||
#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
|
||||
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
|
||||
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
|
||||
|
||||
#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
|
||||
#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
|
||||
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
|
||||
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
|
||||
|
||||
#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
|
||||
#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
|
||||
#define AES_INSTS { AES } /**< \brief (AES) Instances List */
|
||||
|
||||
#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */
|
||||
#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */
|
||||
#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */
|
||||
|
||||
#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
|
||||
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
|
||||
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
|
||||
|
||||
#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
|
||||
#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
|
||||
#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
|
||||
#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
|
||||
|
||||
#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
|
||||
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
|
||||
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
|
||||
|
||||
#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
|
||||
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
|
||||
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
|
||||
|
||||
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
|
||||
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
|
||||
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
|
||||
|
||||
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
|
||||
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
|
||||
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
|
||||
|
||||
#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
|
||||
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
|
||||
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
|
||||
|
||||
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
|
||||
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
|
||||
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
|
||||
|
||||
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
|
||||
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
|
||||
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
|
||||
|
||||
#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
|
||||
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
|
||||
#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
|
||||
|
||||
#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
|
||||
#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
|
||||
#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
|
||||
|
||||
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
|
||||
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
|
||||
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
|
||||
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
|
||||
#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
|
||||
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
|
||||
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
|
||||
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
|
||||
|
||||
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
|
||||
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
|
||||
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
|
||||
|
||||
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
|
||||
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
|
||||
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
|
||||
|
||||
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
|
||||
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
|
||||
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
|
||||
|
||||
#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
|
||||
#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
|
||||
#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
|
||||
|
||||
#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
|
||||
#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
|
||||
#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
|
||||
|
||||
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
|
||||
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
|
||||
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
|
||||
|
||||
#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
|
||||
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
|
||||
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
|
||||
|
||||
#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
|
||||
#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
|
||||
#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
|
||||
#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
|
||||
|
||||
#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
|
||||
#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
|
||||
#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
|
||||
#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
|
||||
|
||||
#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
|
||||
#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
|
||||
#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
|
||||
|
||||
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
|
||||
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
|
||||
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
|
||||
|
||||
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
|
||||
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
|
||||
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
|
||||
|
||||
#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
|
||||
#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */
|
||||
#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */
|
||||
|
||||
#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
|
||||
#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
|
||||
#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
|
||||
#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
|
||||
#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
|
||||
#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
|
||||
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
|
||||
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
|
||||
|
||||
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
|
||||
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
|
||||
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
|
||||
|
||||
#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
|
||||
#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
|
||||
#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
|
||||
#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
|
||||
#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */
|
||||
#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */
|
||||
|
||||
#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
|
||||
#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
|
||||
#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
|
||||
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
|
||||
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
||||
|
||||
#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
|
||||
#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
|
||||
#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
|
||||
|
||||
#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
|
||||
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
||||
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
||||
|
||||
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
|
||||
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
||||
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
||||
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** PORT DEFINITIONS FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
/** \defgroup SAME51G19A_port PORT Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/same51g19a.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** MEMORY MAPPING DEFINITIONS FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */
|
||||
#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */
|
||||
#define FLASH_PAGE_SIZE 512
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 512
|
||||
#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
|
||||
#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
|
||||
|
||||
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
|
||||
#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
|
||||
#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
|
||||
#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
|
||||
#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
|
||||
#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
|
||||
#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
|
||||
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
|
||||
#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
|
||||
#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
|
||||
#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
|
||||
#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
|
||||
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
|
||||
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
|
||||
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
|
||||
#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
|
||||
#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
|
||||
#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
|
||||
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE _UL_(0x61810305)
|
||||
#define ADC0_TOUCH_LINES_NUM 22
|
||||
#define PORT_GROUPS 2
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** ELECTRICAL DEFINITIONS FOR SAME51G19A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* SAME51G19A_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,48 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_SAME51_H_INCLUDED_
|
||||
#define _SYSTEM_SAME51_H_INCLUDED_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
void SystemInit(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_SAME51_H_INCLUDED */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component version header file
|
||||
*
|
||||
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
|
|
@ -43,7 +43,7 @@
|
|||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 96
|
||||
#define BUILD_NUMBER 134
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
|
|
@ -58,7 +58,7 @@
|
|||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2018-09-21 03:51:18"
|
||||
#define COMPONENT_DATE_STRING "2019-04-09 08:16:19"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for AC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_AC_COMPONENT_
|
||||
#define _SAMD51_AC_COMPONENT_
|
||||
#ifndef _SAME54_AC_COMPONENT_
|
||||
#define _SAME54_AC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_AC Analog Comparators */
|
||||
/** \addtogroup SAME54_AC Analog Comparators */
|
||||
/*@{*/
|
||||
|
||||
#define AC_U2501
|
||||
|
|
@ -595,4 +595,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_AC_COMPONENT_ */
|
||||
#endif /* _SAME54_AC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for ADC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_ADC_COMPONENT_
|
||||
#define _SAMD51_ADC_COMPONENT_
|
||||
#ifndef _SAME54_ADC_COMPONENT_
|
||||
#define _SAME54_ADC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR ADC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_ADC Analog Digital Converter */
|
||||
/** \addtogroup SAME54_ADC Analog Digital Converter */
|
||||
/*@{*/
|
||||
|
||||
#define ADC_U2500
|
||||
|
|
@ -868,4 +868,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_ADC_COMPONENT_ */
|
||||
#endif /* _SAME54_ADC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for AES
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_AES_COMPONENT_
|
||||
#define _SAMD51_AES_COMPONENT_
|
||||
#ifndef _SAME54_AES_COMPONENT_
|
||||
#define _SAME54_AES_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AES */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_AES Advanced Encryption Standard */
|
||||
/** \addtogroup SAME54_AES Advanced Encryption Standard */
|
||||
/*@{*/
|
||||
|
||||
#define AES_U2238
|
||||
|
|
@ -372,4 +372,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_AES_COMPONENT_ */
|
||||
#endif /* _SAME54_AES_COMPONENT_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for CCL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CCL_COMPONENT_
|
||||
#define _SAMD51_CCL_COMPONENT_
|
||||
#ifndef _SAME54_CCL_COMPONENT_
|
||||
#define _SAME54_CCL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR CCL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_CCL Configurable Custom Logic */
|
||||
/** \addtogroup SAME54_CCL Configurable Custom Logic */
|
||||
/*@{*/
|
||||
|
||||
#define CCL_U2225
|
||||
|
|
@ -225,4 +225,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_CCL_COMPONENT_ */
|
||||
#endif /* _SAME54_CCL_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for CMCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CMCC_COMPONENT_
|
||||
#define _SAMD51_CMCC_COMPONENT_
|
||||
#ifndef _SAME54_CMCC_COMPONENT_
|
||||
#define _SAME54_CMCC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR CMCC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */
|
||||
/** \addtogroup SAME54_CMCC Cortex M Cache Controller */
|
||||
/*@{*/
|
||||
|
||||
#define CMCC_U2015
|
||||
|
|
@ -354,4 +354,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_CMCC_COMPONENT_ */
|
||||
#endif /* _SAME54_CMCC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for DAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_DAC_COMPONENT_
|
||||
#define _SAMD51_DAC_COMPONENT_
|
||||
#ifndef _SAME54_DAC_COMPONENT_
|
||||
#define _SAME54_DAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */
|
||||
/** \addtogroup SAME54_DAC Digital-to-Analog Converter */
|
||||
/*@{*/
|
||||
|
||||
#define DAC_U2502
|
||||
|
|
@ -541,4 +541,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_DAC_COMPONENT_ */
|
||||
#endif /* _SAME54_DAC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for DMAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_DMAC_COMPONENT_
|
||||
#define _SAMD51_DMAC_COMPONENT_
|
||||
#ifndef _SAME54_DMAC_COMPONENT_
|
||||
#define _SAME54_DMAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DMAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_DMAC Direct Memory Access Controller */
|
||||
/** \addtogroup SAME54_DMAC Direct Memory Access Controller */
|
||||
/*@{*/
|
||||
|
||||
#define DMAC_U2503
|
||||
|
|
@ -1413,4 +1413,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_DMAC_COMPONENT_ */
|
||||
#endif /* _SAME54_DMAC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for DSU
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_DSU_COMPONENT_
|
||||
#define _SAMD51_DSU_COMPONENT_
|
||||
#ifndef _SAME54_DSU_COMPONENT_
|
||||
#define _SAME54_DSU_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DSU */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_DSU Device Service Unit */
|
||||
/** \addtogroup SAME54_DSU Device Service Unit */
|
||||
/*@{*/
|
||||
|
||||
#define DSU_U2410
|
||||
|
|
@ -113,14 +113,12 @@ typedef union {
|
|||
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
|
||||
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
|
||||
uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */
|
||||
uint8_t TDCCD0:1; /*!< bit: 6 Test Debug Communication Channel 0 Dirty */
|
||||
uint8_t TDCCD1:1; /*!< bit: 7 Test Debug Communication Channel 1 Dirty */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
|
||||
uint8_t :2; /*!< bit: 4.. 5 Reserved */
|
||||
uint8_t TDCCD:2; /*!< bit: 6.. 7 Test Debug Communication Channel x Dirty */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DSU_STATUSB_Type;
|
||||
|
|
@ -144,14 +142,7 @@ typedef union {
|
|||
#define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos)
|
||||
#define DSU_STATUSB_CELCK_Pos 5 /**< \brief (DSU_STATUSB) Chip Erase Locked */
|
||||
#define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos)
|
||||
#define DSU_STATUSB_TDCCD0_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 0 Dirty */
|
||||
#define DSU_STATUSB_TDCCD0 (_U_(1) << DSU_STATUSB_TDCCD0_Pos)
|
||||
#define DSU_STATUSB_TDCCD1_Pos 7 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 1 Dirty */
|
||||
#define DSU_STATUSB_TDCCD1 (_U_(1) << DSU_STATUSB_TDCCD1_Pos)
|
||||
#define DSU_STATUSB_TDCCD_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel x Dirty */
|
||||
#define DSU_STATUSB_TDCCD_Msk (_U_(0x3) << DSU_STATUSB_TDCCD_Pos)
|
||||
#define DSU_STATUSB_TDCCD(value) (DSU_STATUSB_TDCCD_Msk & ((value) << DSU_STATUSB_TDCCD_Pos))
|
||||
#define DSU_STATUSB_MASK _U_(0xFF) /**< \brief (DSU_STATUSB) MASK Register */
|
||||
#define DSU_STATUSB_MASK _U_(0x3F) /**< \brief (DSU_STATUSB) MASK Register */
|
||||
|
||||
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -318,24 +309,6 @@ typedef union {
|
|||
#define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)
|
||||
#define DSU_CFG_MASK _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */
|
||||
|
||||
/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_DCFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */
|
||||
#define DSU_DCFG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */
|
||||
|
||||
#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */
|
||||
#define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos)
|
||||
#define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
|
||||
#define DSU_DCFG_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */
|
||||
|
||||
/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
|
|
@ -648,13 +621,11 @@ typedef struct {
|
|||
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
|
||||
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
|
||||
__IO DSU_CFG_Type CFG; /**< \brief Offset: 0x001C (R/W 32) Configuration */
|
||||
RoReg8 Reserved2[0xD0];
|
||||
__IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
|
||||
RoReg8 Reserved3[0xF08];
|
||||
RoReg8 Reserved2[0xFE0];
|
||||
__I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */
|
||||
__I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */
|
||||
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */
|
||||
RoReg8 Reserved4[0xFC0];
|
||||
RoReg8 Reserved3[0xFC0];
|
||||
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */
|
||||
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
|
||||
__I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */
|
||||
|
|
@ -673,4 +644,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_DSU_COMPONENT_ */
|
||||
#endif /* _SAME54_DSU_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for EIC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_EIC_COMPONENT_
|
||||
#define _SAMD51_EIC_COMPONENT_
|
||||
#ifndef _SAME54_EIC_COMPONENT_
|
||||
#define _SAME54_EIC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR EIC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_EIC External Interrupt Controller */
|
||||
/** \addtogroup SAME54_EIC External Interrupt Controller */
|
||||
/*@{*/
|
||||
|
||||
#define EIC_U2254
|
||||
|
|
@ -494,4 +494,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_EIC_COMPONENT_ */
|
||||
#endif /* _SAME54_EIC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_EVSYS_COMPONENT_
|
||||
#define _SAMD51_EVSYS_COMPONENT_
|
||||
#ifndef _SAME54_EVSYS_COMPONENT_
|
||||
#define _SAME54_EVSYS_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR EVSYS */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_EVSYS Event System Interface */
|
||||
/** \addtogroup SAME54_EVSYS Event System Interface */
|
||||
/*@{*/
|
||||
|
||||
#define EVSYS_U2504
|
||||
|
|
@ -584,4 +584,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_EVSYS_COMPONENT_ */
|
||||
#endif /* _SAME54_EVSYS_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for FREQM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_FREQM_COMPONENT_
|
||||
#define _SAMD51_FREQM_COMPONENT_
|
||||
#ifndef _SAME54_FREQM_COMPONENT_
|
||||
#define _SAME54_FREQM_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR FREQM */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_FREQM Frequency Meter */
|
||||
/** \addtogroup SAME54_FREQM Frequency Meter */
|
||||
/*@{*/
|
||||
|
||||
#define FREQM_U2257
|
||||
|
|
@ -230,4 +230,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_FREQM_COMPONENT_ */
|
||||
#endif /* _SAME54_FREQM_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for GCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_GCLK_COMPONENT_
|
||||
#define _SAMD51_GCLK_COMPONENT_
|
||||
#ifndef _SAME54_GCLK_COMPONENT_
|
||||
#define _SAME54_GCLK_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR GCLK */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_GCLK Generic Clock Generator */
|
||||
/** \addtogroup SAME54_GCLK Generic Clock Generator */
|
||||
/*@{*/
|
||||
|
||||
#define GCLK_U2122
|
||||
|
|
@ -269,4 +269,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_GCLK_COMPONENT_ */
|
||||
#endif /* _SAME54_GCLK_COMPONENT_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for HMATRIXB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_HMATRIXB_COMPONENT_
|
||||
#define _SAMD51_HMATRIXB_COMPONENT_
|
||||
#ifndef _SAME54_HMATRIXB_COMPONENT_
|
||||
#define _SAME54_HMATRIXB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR HMATRIXB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_HMATRIXB HSB Matrix */
|
||||
/** \addtogroup SAME54_HMATRIXB HSB Matrix */
|
||||
/*@{*/
|
||||
|
||||
#define HMATRIXB_I7638
|
||||
|
|
@ -81,4 +81,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_HMATRIXB_COMPONENT_ */
|
||||
#endif /* _SAME54_HMATRIXB_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for I2S
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_I2S_COMPONENT_
|
||||
#define _SAMD51_I2S_COMPONENT_
|
||||
#ifndef _SAME54_I2S_COMPONENT_
|
||||
#define _SAME54_I2S_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR I2S */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_I2S Inter-IC Sound Interface */
|
||||
/** \addtogroup SAME54_I2S Inter-IC Sound Interface */
|
||||
/*@{*/
|
||||
|
||||
#define I2S_U2224
|
||||
|
|
@ -744,4 +744,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_I2S_COMPONENT_ */
|
||||
#endif /* _SAME54_I2S_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for ICM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_ICM_COMPONENT_
|
||||
#define _SAMD51_ICM_COMPONENT_
|
||||
#ifndef _SAME54_ICM_COMPONENT_
|
||||
#define _SAME54_ICM_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR ICM */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_ICM Integrity Check Monitor */
|
||||
/** \addtogroup SAME54_ICM Integrity Check Monitor */
|
||||
/*@{*/
|
||||
|
||||
#define ICM_U2010
|
||||
|
|
@ -579,4 +579,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_ICM_COMPONENT_ */
|
||||
#endif /* _SAME54_ICM_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for MCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_MCLK_COMPONENT_
|
||||
#define _SAMD51_MCLK_COMPONENT_
|
||||
#ifndef _SAME54_MCLK_COMPONENT_
|
||||
#define _SAME54_MCLK_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR MCLK */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_MCLK Main Clock */
|
||||
/** \addtogroup SAME54_MCLK Main Clock */
|
||||
/*@{*/
|
||||
|
||||
#define MCLK_U2408
|
||||
|
|
@ -165,10 +165,11 @@ typedef union {
|
|||
uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */
|
||||
uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */
|
||||
uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */
|
||||
uint32_t :1; /*!< bit: 14 Reserved */
|
||||
uint32_t GMAC_:1; /*!< bit: 14 GMAC AHB Clock Mask */
|
||||
uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */
|
||||
uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */
|
||||
uint32_t :2; /*!< bit: 17..18 Reserved */
|
||||
uint32_t CAN0_:1; /*!< bit: 17 CAN0 AHB Clock Mask */
|
||||
uint32_t CAN1_:1; /*!< bit: 18 CAN1 AHB Clock Mask */
|
||||
uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */
|
||||
uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */
|
||||
uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */
|
||||
|
|
@ -211,10 +212,16 @@ typedef union {
|
|||
#define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
|
||||
#define MCLK_AHBMASK_QSPI_Pos 13 /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
|
||||
#define MCLK_AHBMASK_GMAC_Pos 14 /**< \brief (MCLK_AHBMASK) GMAC AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
|
||||
#define MCLK_AHBMASK_SDHC0_Pos 15 /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
|
||||
#define MCLK_AHBMASK_SDHC1_Pos 16 /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
|
||||
#define MCLK_AHBMASK_CAN0_Pos 17 /**< \brief (MCLK_AHBMASK) CAN0 AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
|
||||
#define MCLK_AHBMASK_CAN1_Pos 18 /**< \brief (MCLK_AHBMASK) CAN1 AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
|
||||
#define MCLK_AHBMASK_ICM_Pos 19 /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
|
||||
#define MCLK_AHBMASK_PUKCC_Pos 20 /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
|
||||
|
|
@ -225,7 +232,7 @@ typedef union {
|
|||
#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
|
||||
#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23 /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
|
||||
#define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
|
||||
#define MCLK_AHBMASK_MASK _U_(0x00F9BFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
|
||||
#define MCLK_AHBMASK_MASK _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
|
||||
|
||||
/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -352,7 +359,8 @@ typedef union {
|
|||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :3; /*!< bit: 0.. 2 Reserved */
|
||||
uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Clock Enable */
|
||||
uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */
|
||||
uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */
|
||||
uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */
|
||||
|
|
@ -374,6 +382,8 @@ typedef union {
|
|||
#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */
|
||||
#define MCLK_APBCMASK_RESETVALUE _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
|
||||
|
||||
#define MCLK_APBCMASK_GMAC_Pos 2 /**< \brief (MCLK_APBCMASK) GMAC APB Clock Enable */
|
||||
#define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
|
||||
#define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
|
||||
#define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
|
||||
#define MCLK_APBCMASK_TCC3_Pos 4 /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
|
||||
|
|
@ -396,7 +406,7 @@ typedef union {
|
|||
#define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
|
||||
#define MCLK_APBCMASK_CCL_Pos 14 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
|
||||
#define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
|
||||
#define MCLK_APBCMASK_MASK _U_(0x00006FF8) /**< \brief (MCLK_APBCMASK) MASK Register */
|
||||
#define MCLK_APBCMASK_MASK _U_(0x00006FFC) /**< \brief (MCLK_APBCMASK) MASK Register */
|
||||
|
||||
/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -469,4 +479,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_MCLK_COMPONENT_ */
|
||||
#endif /* _SAME54_MCLK_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_NVMCTRL_COMPONENT_
|
||||
#define _SAMD51_NVMCTRL_COMPONENT_
|
||||
#ifndef _SAME54_NVMCTRL_COMPONENT_
|
||||
#define _SAME54_NVMCTRL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR NVMCTRL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_NVMCTRL Non-Volatile Memory Controller */
|
||||
/** \addtogroup SAME54_NVMCTRL Non-Volatile Memory Controller */
|
||||
/*@{*/
|
||||
|
||||
#define NVMCTRL_U2409
|
||||
|
|
@ -647,24 +647,6 @@ typedef struct {
|
|||
#define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
|
||||
#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
|
||||
|
||||
#define FUSES_BOD12USERLEVEL_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD12USERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BOD12 User Level */
|
||||
#define FUSES_BOD12USERLEVEL_Msk (_U_(0x3F) << FUSES_BOD12USERLEVEL_Pos)
|
||||
#define FUSES_BOD12USERLEVEL(value) (FUSES_BOD12USERLEVEL_Msk & ((value) << FUSES_BOD12USERLEVEL_Pos))
|
||||
|
||||
#define FUSES_BOD12_ACTION_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD12_ACTION_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Action */
|
||||
#define FUSES_BOD12_ACTION_Msk (_U_(0x3) << FUSES_BOD12_ACTION_Pos)
|
||||
#define FUSES_BOD12_ACTION(value) (FUSES_BOD12_ACTION_Msk & ((value) << FUSES_BOD12_ACTION_Pos))
|
||||
|
||||
#define FUSES_BOD12_DIS_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD12_DIS_Pos 16 /**< \brief (NVMCTRL_USER) BOD12 Disable */
|
||||
#define FUSES_BOD12_DIS_Msk (_U_(0x1) << FUSES_BOD12_DIS_Pos)
|
||||
|
||||
#define FUSES_BOD12_HYST_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD12_HYST_Pos 25 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */
|
||||
#define FUSES_BOD12_HYST_Msk (_U_(0x1) << FUSES_BOD12_HYST_Pos)
|
||||
|
||||
#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD33USERLEVEL_Pos 1 /**< \brief (NVMCTRL_USER) BOD33 User Level */
|
||||
#define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
|
||||
|
|
@ -802,4 +784,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_NVMCTRL_COMPONENT_ */
|
||||
#endif /* _SAME54_NVMCTRL_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for OSC32KCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_OSC32KCTRL_COMPONENT_
|
||||
#define _SAMD51_OSC32KCTRL_COMPONENT_
|
||||
#ifndef _SAME54_OSC32KCTRL_COMPONENT_
|
||||
#define _SAME54_OSC32KCTRL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR OSC32KCTRL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_OSC32KCTRL 32kHz Oscillators Control */
|
||||
/** \addtogroup SAME54_OSC32KCTRL 32kHz Oscillators Control */
|
||||
/*@{*/
|
||||
|
||||
#define OSC32KCTRL_U2400
|
||||
|
|
@ -300,4 +300,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_OSC32KCTRL_COMPONENT_ */
|
||||
#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for OSCCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_OSCCTRL_COMPONENT_
|
||||
#define _SAMD51_OSCCTRL_COMPONENT_
|
||||
#ifndef _SAME54_OSCCTRL_COMPONENT_
|
||||
#define _SAME54_OSCCTRL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR OSCCTRL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_OSCCTRL Oscillators Control */
|
||||
/** \addtogroup SAME54_OSCCTRL Oscillators Control */
|
||||
/*@{*/
|
||||
|
||||
#define OSCCTRL_U2401
|
||||
|
|
@ -790,4 +790,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_OSCCTRL_COMPONENT_ */
|
||||
#endif /* _SAME54_OSCCTRL_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PAC_COMPONENT_
|
||||
#define _SAMD51_PAC_COMPONENT_
|
||||
#ifndef _SAME54_PAC_COMPONENT_
|
||||
#define _SAME54_PAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_PAC Peripheral Access Controller */
|
||||
/** \addtogroup SAME54_PAC Peripheral Access Controller */
|
||||
/*@{*/
|
||||
|
||||
#define PAC_U2120
|
||||
|
|
@ -316,7 +316,9 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
|
|||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint32_t :3; /*!< bit: 0.. 2 Reserved */
|
||||
__I uint32_t CAN0_:1; /*!< bit: 0 CAN0 */
|
||||
__I uint32_t CAN1_:1; /*!< bit: 1 CAN1 */
|
||||
__I uint32_t GMAC_:1; /*!< bit: 2 GMAC */
|
||||
__I uint32_t TCC2_:1; /*!< bit: 3 TCC2 */
|
||||
__I uint32_t TCC3_:1; /*!< bit: 4 TCC3 */
|
||||
__I uint32_t TC4_:1; /*!< bit: 5 TC4 */
|
||||
|
|
@ -338,6 +340,12 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
|
|||
#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
|
||||
#define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
|
||||
|
||||
#define PAC_INTFLAGC_CAN0_Pos 0 /**< \brief (PAC_INTFLAGC) CAN0 */
|
||||
#define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos)
|
||||
#define PAC_INTFLAGC_CAN1_Pos 1 /**< \brief (PAC_INTFLAGC) CAN1 */
|
||||
#define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos)
|
||||
#define PAC_INTFLAGC_GMAC_Pos 2 /**< \brief (PAC_INTFLAGC) GMAC */
|
||||
#define PAC_INTFLAGC_GMAC (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos)
|
||||
#define PAC_INTFLAGC_TCC2_Pos 3 /**< \brief (PAC_INTFLAGC) TCC2 */
|
||||
#define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
|
||||
#define PAC_INTFLAGC_TCC3_Pos 4 /**< \brief (PAC_INTFLAGC) TCC3 */
|
||||
|
|
@ -362,7 +370,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
|
|||
#define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
|
||||
#define PAC_INTFLAGC_CCL_Pos 14 /**< \brief (PAC_INTFLAGC) CCL */
|
||||
#define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
|
||||
#define PAC_INTFLAGC_MASK _U_(0x00007FF8) /**< \brief (PAC_INTFLAGC) MASK Register */
|
||||
#define PAC_INTFLAGC_MASK _U_(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */
|
||||
|
||||
/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -544,7 +552,9 @@ typedef union {
|
|||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :3; /*!< bit: 0.. 2 Reserved */
|
||||
uint32_t CAN0_:1; /*!< bit: 0 CAN0 APB Protect Enable */
|
||||
uint32_t CAN1_:1; /*!< bit: 1 CAN1 APB Protect Enable */
|
||||
uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Protect Enable */
|
||||
uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Protect Enable */
|
||||
uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Protect Enable */
|
||||
uint32_t TC4_:1; /*!< bit: 5 TC4 APB Protect Enable */
|
||||
|
|
@ -566,6 +576,12 @@ typedef union {
|
|||
#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
|
||||
#define PAC_STATUSC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
|
||||
|
||||
#define PAC_STATUSC_CAN0_Pos 0 /**< \brief (PAC_STATUSC) CAN0 APB Protect Enable */
|
||||
#define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos)
|
||||
#define PAC_STATUSC_CAN1_Pos 1 /**< \brief (PAC_STATUSC) CAN1 APB Protect Enable */
|
||||
#define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos)
|
||||
#define PAC_STATUSC_GMAC_Pos 2 /**< \brief (PAC_STATUSC) GMAC APB Protect Enable */
|
||||
#define PAC_STATUSC_GMAC (_U_(0x1) << PAC_STATUSC_GMAC_Pos)
|
||||
#define PAC_STATUSC_TCC2_Pos 3 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
|
||||
#define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
|
||||
#define PAC_STATUSC_TCC3_Pos 4 /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */
|
||||
|
|
@ -590,7 +606,7 @@ typedef union {
|
|||
#define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
|
||||
#define PAC_STATUSC_CCL_Pos 14 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
|
||||
#define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
|
||||
#define PAC_STATUSC_MASK _U_(0x00007FF8) /**< \brief (PAC_STATUSC) MASK Register */
|
||||
#define PAC_STATUSC_MASK _U_(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */
|
||||
|
||||
/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -667,4 +683,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_PAC_COMPONENT_ */
|
||||
#endif /* _SAME54_PAC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PCC_COMPONENT_
|
||||
#define _SAMD51_PCC_COMPONENT_
|
||||
#ifndef _SAME54_PCC_COMPONENT_
|
||||
#define _SAME54_PCC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PCC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_PCC Parallel Capture Controller */
|
||||
/** \addtogroup SAME54_PCC Parallel Capture Controller */
|
||||
/*@{*/
|
||||
|
||||
#define PCC_U2017
|
||||
|
|
@ -248,4 +248,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_PCC_COMPONENT_ */
|
||||
#endif /* _SAME54_PCC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PDEC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PDEC_COMPONENT_
|
||||
#define _SAMD51_PDEC_COMPONENT_
|
||||
#ifndef _SAME54_PDEC_COMPONENT_
|
||||
#define _SAME54_PDEC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PDEC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_PDEC Quadrature Decodeur */
|
||||
/** \addtogroup SAME54_PDEC Quadrature Decodeur */
|
||||
/*@{*/
|
||||
|
||||
#define PDEC_U2263
|
||||
|
|
@ -723,4 +723,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_PDEC_COMPONENT_ */
|
||||
#endif /* _SAME54_PDEC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PM_COMPONENT_
|
||||
#define _SAMD51_PM_COMPONENT_
|
||||
#ifndef _SAME54_PM_COMPONENT_
|
||||
#define _SAME54_PM_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PM */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_PM Power Manager */
|
||||
/** \addtogroup SAME54_PM Power Manager */
|
||||
/*@{*/
|
||||
|
||||
#define PM_U2406
|
||||
|
|
@ -258,4 +258,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_PM_COMPONENT_ */
|
||||
#endif /* _SAME54_PM_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PORT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PORT_COMPONENT_
|
||||
#define _SAMD51_PORT_COMPONENT_
|
||||
#ifndef _SAME54_PORT_COMPONENT_
|
||||
#define _SAME54_PORT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PORT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_PORT Port Module */
|
||||
/** \addtogroup SAME54_PORT Port Module */
|
||||
/*@{*/
|
||||
|
||||
#define PORT_U2210
|
||||
|
|
@ -411,4 +411,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_PORT_COMPONENT_ */
|
||||
#endif /* _SAME54_PORT_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for QSPI
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_QSPI_COMPONENT_
|
||||
#define _SAMD51_QSPI_COMPONENT_
|
||||
#ifndef _SAME54_QSPI_COMPONENT_
|
||||
#define _SAME54_QSPI_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR QSPI */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_QSPI Quad SPI interface */
|
||||
/** \addtogroup SAME54_QSPI Quad SPI interface */
|
||||
/*@{*/
|
||||
|
||||
#define QSPI_U2008
|
||||
|
|
@ -525,4 +525,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_QSPI_COMPONENT_ */
|
||||
#endif /* _SAME54_QSPI_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for RAMECC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_RAMECC_COMPONENT_
|
||||
#define _SAMD51_RAMECC_COMPONENT_
|
||||
#ifndef _SAME54_RAMECC_COMPONENT_
|
||||
#define _SAME54_RAMECC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR RAMECC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_RAMECC RAM ECC */
|
||||
/** \addtogroup SAME54_RAMECC RAM ECC */
|
||||
/*@{*/
|
||||
|
||||
#define RAMECC_U2268
|
||||
|
|
@ -175,4 +175,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_RAMECC_COMPONENT_ */
|
||||
#endif /* _SAME54_RAMECC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for RSTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_RSTC_COMPONENT_
|
||||
#define _SAMD51_RSTC_COMPONENT_
|
||||
#ifndef _SAME54_RSTC_COMPONENT_
|
||||
#define _SAME54_RSTC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR RSTC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_RSTC Reset Controller */
|
||||
/** \addtogroup SAME54_RSTC Reset Controller */
|
||||
/*@{*/
|
||||
|
||||
#define RSTC_U2239
|
||||
|
|
@ -112,4 +112,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_RSTC_COMPONENT_ */
|
||||
#endif /* _SAME54_RSTC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for RTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_RTC_COMPONENT_
|
||||
#define _SAMD51_RTC_COMPONENT_
|
||||
#ifndef _SAME54_RTC_COMPONENT_
|
||||
#define _SAME54_RTC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR RTC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_RTC Real-Time Counter */
|
||||
/** \addtogroup SAME54_RTC Real-Time Counter */
|
||||
/*@{*/
|
||||
|
||||
#define RTC_U2250
|
||||
|
|
@ -2095,4 +2095,4 @@ typedef union {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_RTC_COMPONENT_ */
|
||||
#endif /* _SAME54_RTC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for SDHC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SDHC_COMPONENT_
|
||||
#define _SAMD51_SDHC_COMPONENT_
|
||||
#ifndef _SAME54_SDHC_COMPONENT_
|
||||
#define _SAME54_SDHC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR SDHC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_SDHC SD/MMC Host Controller */
|
||||
/** \addtogroup SAME54_SDHC SD/MMC Host Controller */
|
||||
/*@{*/
|
||||
|
||||
#define SDHC_U2011
|
||||
|
|
@ -2596,4 +2596,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_SDHC_COMPONENT_ */
|
||||
#endif /* _SAME54_SDHC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for SERCOM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM_COMPONENT_
|
||||
#define _SAMD51_SERCOM_COMPONENT_
|
||||
#ifndef _SAME54_SERCOM_COMPONENT_
|
||||
#define _SAME54_SERCOM_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR SERCOM */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_SERCOM Serial Communication Interface */
|
||||
/** \addtogroup SAME54_SERCOM Serial Communication Interface */
|
||||
/*@{*/
|
||||
|
||||
#define SERCOM_U2201
|
||||
|
|
@ -1677,4 +1677,4 @@ typedef union {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_SERCOM_COMPONENT_ */
|
||||
#endif /* _SAME54_SERCOM_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for SUPC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SUPC_COMPONENT_
|
||||
#define _SAMD51_SUPC_COMPONENT_
|
||||
#ifndef _SAME54_SUPC_COMPONENT_
|
||||
#define _SAME54_SUPC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR SUPC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_SUPC Supply Controller */
|
||||
/** \addtogroup SAME54_SUPC Supply Controller */
|
||||
/*@{*/
|
||||
|
||||
#define SUPC_U2407
|
||||
|
|
@ -46,10 +46,7 @@ typedef union {
|
|||
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
|
||||
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
|
||||
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
|
||||
uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
|
||||
uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
|
||||
uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
|
||||
uint32_t :1; /*!< bit: 9 Reserved */
|
||||
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
|
||||
|
|
@ -68,17 +65,11 @@ typedef union {
|
|||
#define SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)
|
||||
#define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */
|
||||
#define SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)
|
||||
#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */
|
||||
#define SUPC_INTENCLR_BOD12RDY (_U_(0x1) << SUPC_INTENCLR_BOD12RDY_Pos)
|
||||
#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */
|
||||
#define SUPC_INTENCLR_BOD12DET (_U_(0x1) << SUPC_INTENCLR_BOD12DET_Pos)
|
||||
#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */
|
||||
#define SUPC_INTENCLR_B12SRDY (_U_(0x1) << SUPC_INTENCLR_B12SRDY_Pos)
|
||||
#define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */
|
||||
#define SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)
|
||||
#define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */
|
||||
#define SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)
|
||||
#define SUPC_INTENCLR_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENCLR) MASK Register */
|
||||
#define SUPC_INTENCLR_MASK _U_(0x00000507) /**< \brief (SUPC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -87,10 +78,7 @@ typedef union {
|
|||
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
|
||||
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
|
||||
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
|
||||
uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
|
||||
uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
|
||||
uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
|
||||
uint32_t :1; /*!< bit: 9 Reserved */
|
||||
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
|
||||
|
|
@ -109,17 +97,11 @@ typedef union {
|
|||
#define SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)
|
||||
#define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */
|
||||
#define SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)
|
||||
#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */
|
||||
#define SUPC_INTENSET_BOD12RDY (_U_(0x1) << SUPC_INTENSET_BOD12RDY_Pos)
|
||||
#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */
|
||||
#define SUPC_INTENSET_BOD12DET (_U_(0x1) << SUPC_INTENSET_BOD12DET_Pos)
|
||||
#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */
|
||||
#define SUPC_INTENSET_B12SRDY (_U_(0x1) << SUPC_INTENSET_B12SRDY_Pos)
|
||||
#define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */
|
||||
#define SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)
|
||||
#define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */
|
||||
#define SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)
|
||||
#define SUPC_INTENSET_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENSET) MASK Register */
|
||||
#define SUPC_INTENSET_MASK _U_(0x00000507) /**< \brief (SUPC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -128,10 +110,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
|
|||
__I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
|
||||
__I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
|
||||
__I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
|
||||
__I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
|
||||
__I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
|
||||
__I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
|
||||
__I uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
__I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
|
||||
__I uint32_t :1; /*!< bit: 9 Reserved */
|
||||
__I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
|
||||
|
|
@ -150,17 +129,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
|
|||
#define SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)
|
||||
#define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */
|
||||
#define SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)
|
||||
#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */
|
||||
#define SUPC_INTFLAG_BOD12RDY (_U_(0x1) << SUPC_INTFLAG_BOD12RDY_Pos)
|
||||
#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */
|
||||
#define SUPC_INTFLAG_BOD12DET (_U_(0x1) << SUPC_INTFLAG_BOD12DET_Pos)
|
||||
#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */
|
||||
#define SUPC_INTFLAG_B12SRDY (_U_(0x1) << SUPC_INTFLAG_B12SRDY_Pos)
|
||||
#define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */
|
||||
#define SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)
|
||||
#define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */
|
||||
#define SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)
|
||||
#define SUPC_INTFLAG_MASK _U_(0x0000053F) /**< \brief (SUPC_INTFLAG) MASK Register */
|
||||
#define SUPC_INTFLAG_MASK _U_(0x00000507) /**< \brief (SUPC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -169,10 +142,7 @@ typedef union {
|
|||
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
|
||||
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
|
||||
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
|
||||
uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
|
||||
uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
|
||||
uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
|
||||
uint32_t :1; /*!< bit: 9 Reserved */
|
||||
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
|
||||
|
|
@ -191,17 +161,11 @@ typedef union {
|
|||
#define SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)
|
||||
#define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */
|
||||
#define SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)
|
||||
#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */
|
||||
#define SUPC_STATUS_BOD12RDY (_U_(0x1) << SUPC_STATUS_BOD12RDY_Pos)
|
||||
#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */
|
||||
#define SUPC_STATUS_BOD12DET (_U_(0x1) << SUPC_STATUS_BOD12DET_Pos)
|
||||
#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */
|
||||
#define SUPC_STATUS_B12SRDY (_U_(0x1) << SUPC_STATUS_B12SRDY_Pos)
|
||||
#define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */
|
||||
#define SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)
|
||||
#define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */
|
||||
#define SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)
|
||||
#define SUPC_STATUS_MASK _U_(0x0000053F) /**< \brief (SUPC_STATUS) MASK Register */
|
||||
#define SUPC_STATUS_MASK _U_(0x00000507) /**< \brief (SUPC_STATUS) MASK Register */
|
||||
|
||||
/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -278,89 +242,6 @@ typedef union {
|
|||
#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
|
||||
#define SUPC_BOD33_MASK _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */
|
||||
|
||||
/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */
|
||||
uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */
|
||||
uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */
|
||||
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
|
||||
uint32_t :1; /*!< bit: 7 Reserved */
|
||||
uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */
|
||||
uint32_t :3; /*!< bit: 9..11 Reserved */
|
||||
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
|
||||
uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */
|
||||
uint32_t :10; /*!< bit: 22..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} SUPC_BOD12_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */
|
||||
#define SUPC_BOD12_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */
|
||||
|
||||
#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */
|
||||
#define SUPC_BOD12_ENABLE (_U_(0x1) << SUPC_BOD12_ENABLE_Pos)
|
||||
#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */
|
||||
#define SUPC_BOD12_HYST (_U_(0x1) << SUPC_BOD12_HYST_Pos)
|
||||
#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */
|
||||
#define SUPC_BOD12_ACTION_Msk (_U_(0x3) << SUPC_BOD12_ACTION_Pos)
|
||||
#define SUPC_BOD12_ACTION(value) (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))
|
||||
#define SUPC_BOD12_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD12) No action */
|
||||
#define SUPC_BOD12_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD12) The BOD12 generates a reset */
|
||||
#define SUPC_BOD12_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */
|
||||
#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos)
|
||||
#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos)
|
||||
#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos)
|
||||
#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */
|
||||
#define SUPC_BOD12_STDBYCFG (_U_(0x1) << SUPC_BOD12_STDBYCFG_Pos)
|
||||
#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */
|
||||
#define SUPC_BOD12_RUNSTDBY (_U_(0x1) << SUPC_BOD12_RUNSTDBY_Pos)
|
||||
#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */
|
||||
#define SUPC_BOD12_ACTCFG (_U_(0x1) << SUPC_BOD12_ACTCFG_Pos)
|
||||
#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */
|
||||
#define SUPC_BOD12_PSEL_Msk (_U_(0xF) << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL(value) (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))
|
||||
#define SUPC_BOD12_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BOD12) Divide clock by 2 */
|
||||
#define SUPC_BOD12_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD12) Divide clock by 4 */
|
||||
#define SUPC_BOD12_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD12) Divide clock by 8 */
|
||||
#define SUPC_BOD12_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD12) Divide clock by 16 */
|
||||
#define SUPC_BOD12_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD12) Divide clock by 32 */
|
||||
#define SUPC_BOD12_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD12) Divide clock by 64 */
|
||||
#define SUPC_BOD12_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD12) Divide clock by 128 */
|
||||
#define SUPC_BOD12_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD12) Divide clock by 256 */
|
||||
#define SUPC_BOD12_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BOD12) Divide clock by 512 */
|
||||
#define SUPC_BOD12_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BOD12) Divide clock by 1024 */
|
||||
#define SUPC_BOD12_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BOD12) Divide clock by 2048 */
|
||||
#define SUPC_BOD12_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BOD12) Divide clock by 4096 */
|
||||
#define SUPC_BOD12_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BOD12) Divide clock by 8192 */
|
||||
#define SUPC_BOD12_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BOD12) Divide clock by 16384 */
|
||||
#define SUPC_BOD12_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BOD12) Divide clock by 32768 */
|
||||
#define SUPC_BOD12_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BOD12) Divide clock by 65536 */
|
||||
#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos)
|
||||
#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */
|
||||
#define SUPC_BOD12_LEVEL_Msk (_U_(0x3F) << SUPC_BOD12_LEVEL_Pos)
|
||||
#define SUPC_BOD12_LEVEL(value) (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))
|
||||
#define SUPC_BOD12_MASK _U_(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */
|
||||
|
||||
/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
|
|
@ -540,7 +421,7 @@ typedef struct {
|
|||
__IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
|
||||
__I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
|
||||
__IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */
|
||||
__IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */
|
||||
RoReg8 Reserved1[0x4];
|
||||
__IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */
|
||||
__IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */
|
||||
__IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */
|
||||
|
|
@ -551,4 +432,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_SUPC_COMPONENT_ */
|
||||
#endif /* _SAME54_SUPC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for TC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_TC_COMPONENT_
|
||||
#define _SAMD51_TC_COMPONENT_
|
||||
#ifndef _SAME54_TC_COMPONENT_
|
||||
#define _SAME54_TC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR TC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_TC Basic Timer Counter */
|
||||
/** \addtogroup SAME54_TC Basic Timer Counter */
|
||||
/*@{*/
|
||||
|
||||
#define TC_U2249
|
||||
|
|
@ -848,4 +848,4 @@ typedef union {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_TC_COMPONENT_ */
|
||||
#endif /* _SAME54_TC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for TCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_TCC_COMPONENT_
|
||||
#define _SAMD51_TCC_COMPONENT_
|
||||
#ifndef _SAME54_TCC_COMPONENT_
|
||||
#define _SAME54_TCC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR TCC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_TCC Timer Counter Control */
|
||||
/** \addtogroup SAME54_TCC Timer Counter Control */
|
||||
/*@{*/
|
||||
|
||||
#define TCC_U2213
|
||||
|
|
@ -1759,4 +1759,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_TCC_COMPONENT_ */
|
||||
#endif /* _SAME54_TCC_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for TRNG
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_TRNG_COMPONENT_
|
||||
#define _SAMD51_TRNG_COMPONENT_
|
||||
#ifndef _SAME54_TRNG_COMPONENT_
|
||||
#define _SAME54_TRNG_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR TRNG */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_TRNG True Random Generator */
|
||||
/** \addtogroup SAME54_TRNG True Random Generator */
|
||||
/*@{*/
|
||||
|
||||
#define TRNG_U2242
|
||||
|
|
@ -169,4 +169,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_TRNG_COMPONENT_ */
|
||||
#endif /* _SAME54_TRNG_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for USB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_USB_COMPONENT_
|
||||
#define _SAMD51_USB_COMPONENT_
|
||||
#ifndef _SAME54_USB_COMPONENT_
|
||||
#define _SAME54_USB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR USB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_USB Universal Serial Bus */
|
||||
/** \addtogroup SAME54_USB Universal Serial Bus */
|
||||
/*@{*/
|
||||
|
||||
#define USB_U2222
|
||||
|
|
@ -1774,4 +1774,4 @@ typedef union {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_USB_COMPONENT_ */
|
||||
#endif /* _SAME54_USB_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for WDT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,13 +27,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_WDT_COMPONENT_
|
||||
#define _SAMD51_WDT_COMPONENT_
|
||||
#ifndef _SAME54_WDT_COMPONENT_
|
||||
#define _SAME54_WDT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR WDT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_WDT Watchdog Timer */
|
||||
/** \addtogroup SAME54_WDT Watchdog Timer */
|
||||
/*@{*/
|
||||
|
||||
#define WDT_U2251
|
||||
|
|
@ -297,4 +297,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_WDT_COMPONENT_ */
|
||||
#endif /* _SAME54_WDT_COMPONENT_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for AC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_AC_INSTANCE_
|
||||
#define _SAMD51_AC_INSTANCE_
|
||||
#ifndef _SAME54_AC_INSTANCE_
|
||||
#define _SAME54_AC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for AC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -76,4 +76,4 @@
|
|||
#define AC_PAIRS 1 // Number of pairs of comparators
|
||||
#define AC_SPEED_LEVELS 2 // Number of speed values
|
||||
|
||||
#endif /* _SAMD51_AC_INSTANCE_ */
|
||||
#endif /* _SAME54_AC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for ADC0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_ADC0_INSTANCE_
|
||||
#define _SAMD51_ADC0_INSTANCE_
|
||||
#ifndef _SAME54_ADC0_INSTANCE_
|
||||
#define _SAME54_ADC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -96,4 +96,4 @@
|
|||
#define ADC0_PTAT 28 // MUXPOS value to select PTAT
|
||||
#define ADC0_TOUCH_IMPLEMENTED 1 // TOUCH implemented or not
|
||||
|
||||
#endif /* _SAMD51_ADC0_INSTANCE_ */
|
||||
#endif /* _SAME54_ADC0_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for ADC1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_ADC1_INSTANCE_
|
||||
#define _SAMD51_ADC1_INSTANCE_
|
||||
#ifndef _SAME54_ADC1_INSTANCE_
|
||||
#define _SAME54_ADC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -97,4 +97,4 @@
|
|||
#define ADC1_TOUCH_IMPLEMENTED 0 // TOUCH implemented or not
|
||||
#define ADC1_TOUCH_LINES_NUM 1 // Number of touch lines
|
||||
|
||||
#endif /* _SAMD51_ADC1_INSTANCE_ */
|
||||
#endif /* _SAME54_ADC1_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for AES
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_AES_INSTANCE_
|
||||
#define _SAMD51_AES_INSTANCE_
|
||||
#ifndef _SAME54_AES_INSTANCE_
|
||||
#define _SAME54_AES_INSTANCE_
|
||||
|
||||
/* ========== Register definition for AES peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -102,4 +102,4 @@
|
|||
#define AES_GCM 1 // GCM
|
||||
#define AES_KEYLEN 2 // Key Length
|
||||
|
||||
#endif /* _SAMD51_AES_INSTANCE_ */
|
||||
#endif /* _SAME54_AES_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for CAN0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAME54_CAN0_INSTANCE_
|
||||
#define _SAME54_CAN0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for CAN0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_CAN0_CREL (0x42000000) /**< \brief (CAN0) Core Release */
|
||||
#define REG_CAN0_ENDN (0x42000004) /**< \brief (CAN0) Endian */
|
||||
#define REG_CAN0_MRCFG (0x42000008) /**< \brief (CAN0) Message RAM Configuration */
|
||||
#define REG_CAN0_DBTP (0x4200000C) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
|
||||
#define REG_CAN0_TEST (0x42000010) /**< \brief (CAN0) Test */
|
||||
#define REG_CAN0_RWD (0x42000014) /**< \brief (CAN0) RAM Watchdog */
|
||||
#define REG_CAN0_CCCR (0x42000018) /**< \brief (CAN0) CC Control */
|
||||
#define REG_CAN0_NBTP (0x4200001C) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
|
||||
#define REG_CAN0_TSCC (0x42000020) /**< \brief (CAN0) Timestamp Counter Configuration */
|
||||
#define REG_CAN0_TSCV (0x42000024) /**< \brief (CAN0) Timestamp Counter Value */
|
||||
#define REG_CAN0_TOCC (0x42000028) /**< \brief (CAN0) Timeout Counter Configuration */
|
||||
#define REG_CAN0_TOCV (0x4200002C) /**< \brief (CAN0) Timeout Counter Value */
|
||||
#define REG_CAN0_ECR (0x42000040) /**< \brief (CAN0) Error Counter */
|
||||
#define REG_CAN0_PSR (0x42000044) /**< \brief (CAN0) Protocol Status */
|
||||
#define REG_CAN0_TDCR (0x42000048) /**< \brief (CAN0) Extended ID Filter Configuration */
|
||||
#define REG_CAN0_IR (0x42000050) /**< \brief (CAN0) Interrupt */
|
||||
#define REG_CAN0_IE (0x42000054) /**< \brief (CAN0) Interrupt Enable */
|
||||
#define REG_CAN0_ILS (0x42000058) /**< \brief (CAN0) Interrupt Line Select */
|
||||
#define REG_CAN0_ILE (0x4200005C) /**< \brief (CAN0) Interrupt Line Enable */
|
||||
#define REG_CAN0_GFC (0x42000080) /**< \brief (CAN0) Global Filter Configuration */
|
||||
#define REG_CAN0_SIDFC (0x42000084) /**< \brief (CAN0) Standard ID Filter Configuration */
|
||||
#define REG_CAN0_XIDFC (0x42000088) /**< \brief (CAN0) Extended ID Filter Configuration */
|
||||
#define REG_CAN0_XIDAM (0x42000090) /**< \brief (CAN0) Extended ID AND Mask */
|
||||
#define REG_CAN0_HPMS (0x42000094) /**< \brief (CAN0) High Priority Message Status */
|
||||
#define REG_CAN0_NDAT1 (0x42000098) /**< \brief (CAN0) New Data 1 */
|
||||
#define REG_CAN0_NDAT2 (0x4200009C) /**< \brief (CAN0) New Data 2 */
|
||||
#define REG_CAN0_RXF0C (0x420000A0) /**< \brief (CAN0) Rx FIFO 0 Configuration */
|
||||
#define REG_CAN0_RXF0S (0x420000A4) /**< \brief (CAN0) Rx FIFO 0 Status */
|
||||
#define REG_CAN0_RXF0A (0x420000A8) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
|
||||
#define REG_CAN0_RXBC (0x420000AC) /**< \brief (CAN0) Rx Buffer Configuration */
|
||||
#define REG_CAN0_RXF1C (0x420000B0) /**< \brief (CAN0) Rx FIFO 1 Configuration */
|
||||
#define REG_CAN0_RXF1S (0x420000B4) /**< \brief (CAN0) Rx FIFO 1 Status */
|
||||
#define REG_CAN0_RXF1A (0x420000B8) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
|
||||
#define REG_CAN0_RXESC (0x420000BC) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
|
||||
#define REG_CAN0_TXBC (0x420000C0) /**< \brief (CAN0) Tx Buffer Configuration */
|
||||
#define REG_CAN0_TXFQS (0x420000C4) /**< \brief (CAN0) Tx FIFO / Queue Status */
|
||||
#define REG_CAN0_TXESC (0x420000C8) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
|
||||
#define REG_CAN0_TXBRP (0x420000CC) /**< \brief (CAN0) Tx Buffer Request Pending */
|
||||
#define REG_CAN0_TXBAR (0x420000D0) /**< \brief (CAN0) Tx Buffer Add Request */
|
||||
#define REG_CAN0_TXBCR (0x420000D4) /**< \brief (CAN0) Tx Buffer Cancellation Request */
|
||||
#define REG_CAN0_TXBTO (0x420000D8) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
|
||||
#define REG_CAN0_TXBCF (0x420000DC) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
|
||||
#define REG_CAN0_TXBTIE (0x420000E0) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
|
||||
#define REG_CAN0_TXBCIE (0x420000E4) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
|
||||
#define REG_CAN0_TXEFC (0x420000F0) /**< \brief (CAN0) Tx Event FIFO Configuration */
|
||||
#define REG_CAN0_TXEFS (0x420000F4) /**< \brief (CAN0) Tx Event FIFO Status */
|
||||
#define REG_CAN0_TXEFA (0x420000F8) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
|
||||
#else
|
||||
#define REG_CAN0_CREL (*(RoReg *)0x42000000UL) /**< \brief (CAN0) Core Release */
|
||||
#define REG_CAN0_ENDN (*(RoReg *)0x42000004UL) /**< \brief (CAN0) Endian */
|
||||
#define REG_CAN0_MRCFG (*(RwReg *)0x42000008UL) /**< \brief (CAN0) Message RAM Configuration */
|
||||
#define REG_CAN0_DBTP (*(RwReg *)0x4200000CUL) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
|
||||
#define REG_CAN0_TEST (*(RwReg *)0x42000010UL) /**< \brief (CAN0) Test */
|
||||
#define REG_CAN0_RWD (*(RwReg *)0x42000014UL) /**< \brief (CAN0) RAM Watchdog */
|
||||
#define REG_CAN0_CCCR (*(RwReg *)0x42000018UL) /**< \brief (CAN0) CC Control */
|
||||
#define REG_CAN0_NBTP (*(RwReg *)0x4200001CUL) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
|
||||
#define REG_CAN0_TSCC (*(RwReg *)0x42000020UL) /**< \brief (CAN0) Timestamp Counter Configuration */
|
||||
#define REG_CAN0_TSCV (*(RoReg *)0x42000024UL) /**< \brief (CAN0) Timestamp Counter Value */
|
||||
#define REG_CAN0_TOCC (*(RwReg *)0x42000028UL) /**< \brief (CAN0) Timeout Counter Configuration */
|
||||
#define REG_CAN0_TOCV (*(RwReg *)0x4200002CUL) /**< \brief (CAN0) Timeout Counter Value */
|
||||
#define REG_CAN0_ECR (*(RoReg *)0x42000040UL) /**< \brief (CAN0) Error Counter */
|
||||
#define REG_CAN0_PSR (*(RoReg *)0x42000044UL) /**< \brief (CAN0) Protocol Status */
|
||||
#define REG_CAN0_TDCR (*(RwReg *)0x42000048UL) /**< \brief (CAN0) Extended ID Filter Configuration */
|
||||
#define REG_CAN0_IR (*(RwReg *)0x42000050UL) /**< \brief (CAN0) Interrupt */
|
||||
#define REG_CAN0_IE (*(RwReg *)0x42000054UL) /**< \brief (CAN0) Interrupt Enable */
|
||||
#define REG_CAN0_ILS (*(RwReg *)0x42000058UL) /**< \brief (CAN0) Interrupt Line Select */
|
||||
#define REG_CAN0_ILE (*(RwReg *)0x4200005CUL) /**< \brief (CAN0) Interrupt Line Enable */
|
||||
#define REG_CAN0_GFC (*(RwReg *)0x42000080UL) /**< \brief (CAN0) Global Filter Configuration */
|
||||
#define REG_CAN0_SIDFC (*(RwReg *)0x42000084UL) /**< \brief (CAN0) Standard ID Filter Configuration */
|
||||
#define REG_CAN0_XIDFC (*(RwReg *)0x42000088UL) /**< \brief (CAN0) Extended ID Filter Configuration */
|
||||
#define REG_CAN0_XIDAM (*(RwReg *)0x42000090UL) /**< \brief (CAN0) Extended ID AND Mask */
|
||||
#define REG_CAN0_HPMS (*(RoReg *)0x42000094UL) /**< \brief (CAN0) High Priority Message Status */
|
||||
#define REG_CAN0_NDAT1 (*(RwReg *)0x42000098UL) /**< \brief (CAN0) New Data 1 */
|
||||
#define REG_CAN0_NDAT2 (*(RwReg *)0x4200009CUL) /**< \brief (CAN0) New Data 2 */
|
||||
#define REG_CAN0_RXF0C (*(RwReg *)0x420000A0UL) /**< \brief (CAN0) Rx FIFO 0 Configuration */
|
||||
#define REG_CAN0_RXF0S (*(RoReg *)0x420000A4UL) /**< \brief (CAN0) Rx FIFO 0 Status */
|
||||
#define REG_CAN0_RXF0A (*(RwReg *)0x420000A8UL) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
|
||||
#define REG_CAN0_RXBC (*(RwReg *)0x420000ACUL) /**< \brief (CAN0) Rx Buffer Configuration */
|
||||
#define REG_CAN0_RXF1C (*(RwReg *)0x420000B0UL) /**< \brief (CAN0) Rx FIFO 1 Configuration */
|
||||
#define REG_CAN0_RXF1S (*(RoReg *)0x420000B4UL) /**< \brief (CAN0) Rx FIFO 1 Status */
|
||||
#define REG_CAN0_RXF1A (*(RwReg *)0x420000B8UL) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
|
||||
#define REG_CAN0_RXESC (*(RwReg *)0x420000BCUL) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
|
||||
#define REG_CAN0_TXBC (*(RwReg *)0x420000C0UL) /**< \brief (CAN0) Tx Buffer Configuration */
|
||||
#define REG_CAN0_TXFQS (*(RoReg *)0x420000C4UL) /**< \brief (CAN0) Tx FIFO / Queue Status */
|
||||
#define REG_CAN0_TXESC (*(RwReg *)0x420000C8UL) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
|
||||
#define REG_CAN0_TXBRP (*(RoReg *)0x420000CCUL) /**< \brief (CAN0) Tx Buffer Request Pending */
|
||||
#define REG_CAN0_TXBAR (*(RwReg *)0x420000D0UL) /**< \brief (CAN0) Tx Buffer Add Request */
|
||||
#define REG_CAN0_TXBCR (*(RwReg *)0x420000D4UL) /**< \brief (CAN0) Tx Buffer Cancellation Request */
|
||||
#define REG_CAN0_TXBTO (*(RoReg *)0x420000D8UL) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
|
||||
#define REG_CAN0_TXBCF (*(RoReg *)0x420000DCUL) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
|
||||
#define REG_CAN0_TXBTIE (*(RwReg *)0x420000E0UL) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
|
||||
#define REG_CAN0_TXBCIE (*(RwReg *)0x420000E4UL) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
|
||||
#define REG_CAN0_TXEFC (*(RwReg *)0x420000F0UL) /**< \brief (CAN0) Tx Event FIFO Configuration */
|
||||
#define REG_CAN0_TXEFS (*(RoReg *)0x420000F4UL) /**< \brief (CAN0) Tx Event FIFO Status */
|
||||
#define REG_CAN0_TXEFA (*(RwReg *)0x420000F8UL) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for CAN0 peripheral ========== */
|
||||
#define CAN0_CLK_AHB_ID 17 // Index of AHB clock
|
||||
#define CAN0_DMAC_ID_DEBUG 20 // DMA CAN Debug Req
|
||||
#define CAN0_GCLK_ID 27 // Index of Generic Clock
|
||||
#define CAN0_MSG_RAM_ADDR 0x20000000
|
||||
#define CAN0_QOS_RESET_VAL 1 // QOS reset value
|
||||
|
||||
#endif /* _SAME54_CAN0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for CAN1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAME54_CAN1_INSTANCE_
|
||||
#define _SAME54_CAN1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for CAN1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_CAN1_CREL (0x42000400) /**< \brief (CAN1) Core Release */
|
||||
#define REG_CAN1_ENDN (0x42000404) /**< \brief (CAN1) Endian */
|
||||
#define REG_CAN1_MRCFG (0x42000408) /**< \brief (CAN1) Message RAM Configuration */
|
||||
#define REG_CAN1_DBTP (0x4200040C) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
|
||||
#define REG_CAN1_TEST (0x42000410) /**< \brief (CAN1) Test */
|
||||
#define REG_CAN1_RWD (0x42000414) /**< \brief (CAN1) RAM Watchdog */
|
||||
#define REG_CAN1_CCCR (0x42000418) /**< \brief (CAN1) CC Control */
|
||||
#define REG_CAN1_NBTP (0x4200041C) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
|
||||
#define REG_CAN1_TSCC (0x42000420) /**< \brief (CAN1) Timestamp Counter Configuration */
|
||||
#define REG_CAN1_TSCV (0x42000424) /**< \brief (CAN1) Timestamp Counter Value */
|
||||
#define REG_CAN1_TOCC (0x42000428) /**< \brief (CAN1) Timeout Counter Configuration */
|
||||
#define REG_CAN1_TOCV (0x4200042C) /**< \brief (CAN1) Timeout Counter Value */
|
||||
#define REG_CAN1_ECR (0x42000440) /**< \brief (CAN1) Error Counter */
|
||||
#define REG_CAN1_PSR (0x42000444) /**< \brief (CAN1) Protocol Status */
|
||||
#define REG_CAN1_TDCR (0x42000448) /**< \brief (CAN1) Extended ID Filter Configuration */
|
||||
#define REG_CAN1_IR (0x42000450) /**< \brief (CAN1) Interrupt */
|
||||
#define REG_CAN1_IE (0x42000454) /**< \brief (CAN1) Interrupt Enable */
|
||||
#define REG_CAN1_ILS (0x42000458) /**< \brief (CAN1) Interrupt Line Select */
|
||||
#define REG_CAN1_ILE (0x4200045C) /**< \brief (CAN1) Interrupt Line Enable */
|
||||
#define REG_CAN1_GFC (0x42000480) /**< \brief (CAN1) Global Filter Configuration */
|
||||
#define REG_CAN1_SIDFC (0x42000484) /**< \brief (CAN1) Standard ID Filter Configuration */
|
||||
#define REG_CAN1_XIDFC (0x42000488) /**< \brief (CAN1) Extended ID Filter Configuration */
|
||||
#define REG_CAN1_XIDAM (0x42000490) /**< \brief (CAN1) Extended ID AND Mask */
|
||||
#define REG_CAN1_HPMS (0x42000494) /**< \brief (CAN1) High Priority Message Status */
|
||||
#define REG_CAN1_NDAT1 (0x42000498) /**< \brief (CAN1) New Data 1 */
|
||||
#define REG_CAN1_NDAT2 (0x4200049C) /**< \brief (CAN1) New Data 2 */
|
||||
#define REG_CAN1_RXF0C (0x420004A0) /**< \brief (CAN1) Rx FIFO 0 Configuration */
|
||||
#define REG_CAN1_RXF0S (0x420004A4) /**< \brief (CAN1) Rx FIFO 0 Status */
|
||||
#define REG_CAN1_RXF0A (0x420004A8) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
|
||||
#define REG_CAN1_RXBC (0x420004AC) /**< \brief (CAN1) Rx Buffer Configuration */
|
||||
#define REG_CAN1_RXF1C (0x420004B0) /**< \brief (CAN1) Rx FIFO 1 Configuration */
|
||||
#define REG_CAN1_RXF1S (0x420004B4) /**< \brief (CAN1) Rx FIFO 1 Status */
|
||||
#define REG_CAN1_RXF1A (0x420004B8) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
|
||||
#define REG_CAN1_RXESC (0x420004BC) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
|
||||
#define REG_CAN1_TXBC (0x420004C0) /**< \brief (CAN1) Tx Buffer Configuration */
|
||||
#define REG_CAN1_TXFQS (0x420004C4) /**< \brief (CAN1) Tx FIFO / Queue Status */
|
||||
#define REG_CAN1_TXESC (0x420004C8) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
|
||||
#define REG_CAN1_TXBRP (0x420004CC) /**< \brief (CAN1) Tx Buffer Request Pending */
|
||||
#define REG_CAN1_TXBAR (0x420004D0) /**< \brief (CAN1) Tx Buffer Add Request */
|
||||
#define REG_CAN1_TXBCR (0x420004D4) /**< \brief (CAN1) Tx Buffer Cancellation Request */
|
||||
#define REG_CAN1_TXBTO (0x420004D8) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
|
||||
#define REG_CAN1_TXBCF (0x420004DC) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
|
||||
#define REG_CAN1_TXBTIE (0x420004E0) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
|
||||
#define REG_CAN1_TXBCIE (0x420004E4) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
|
||||
#define REG_CAN1_TXEFC (0x420004F0) /**< \brief (CAN1) Tx Event FIFO Configuration */
|
||||
#define REG_CAN1_TXEFS (0x420004F4) /**< \brief (CAN1) Tx Event FIFO Status */
|
||||
#define REG_CAN1_TXEFA (0x420004F8) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
|
||||
#else
|
||||
#define REG_CAN1_CREL (*(RoReg *)0x42000400UL) /**< \brief (CAN1) Core Release */
|
||||
#define REG_CAN1_ENDN (*(RoReg *)0x42000404UL) /**< \brief (CAN1) Endian */
|
||||
#define REG_CAN1_MRCFG (*(RwReg *)0x42000408UL) /**< \brief (CAN1) Message RAM Configuration */
|
||||
#define REG_CAN1_DBTP (*(RwReg *)0x4200040CUL) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
|
||||
#define REG_CAN1_TEST (*(RwReg *)0x42000410UL) /**< \brief (CAN1) Test */
|
||||
#define REG_CAN1_RWD (*(RwReg *)0x42000414UL) /**< \brief (CAN1) RAM Watchdog */
|
||||
#define REG_CAN1_CCCR (*(RwReg *)0x42000418UL) /**< \brief (CAN1) CC Control */
|
||||
#define REG_CAN1_NBTP (*(RwReg *)0x4200041CUL) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
|
||||
#define REG_CAN1_TSCC (*(RwReg *)0x42000420UL) /**< \brief (CAN1) Timestamp Counter Configuration */
|
||||
#define REG_CAN1_TSCV (*(RoReg *)0x42000424UL) /**< \brief (CAN1) Timestamp Counter Value */
|
||||
#define REG_CAN1_TOCC (*(RwReg *)0x42000428UL) /**< \brief (CAN1) Timeout Counter Configuration */
|
||||
#define REG_CAN1_TOCV (*(RwReg *)0x4200042CUL) /**< \brief (CAN1) Timeout Counter Value */
|
||||
#define REG_CAN1_ECR (*(RoReg *)0x42000440UL) /**< \brief (CAN1) Error Counter */
|
||||
#define REG_CAN1_PSR (*(RoReg *)0x42000444UL) /**< \brief (CAN1) Protocol Status */
|
||||
#define REG_CAN1_TDCR (*(RwReg *)0x42000448UL) /**< \brief (CAN1) Extended ID Filter Configuration */
|
||||
#define REG_CAN1_IR (*(RwReg *)0x42000450UL) /**< \brief (CAN1) Interrupt */
|
||||
#define REG_CAN1_IE (*(RwReg *)0x42000454UL) /**< \brief (CAN1) Interrupt Enable */
|
||||
#define REG_CAN1_ILS (*(RwReg *)0x42000458UL) /**< \brief (CAN1) Interrupt Line Select */
|
||||
#define REG_CAN1_ILE (*(RwReg *)0x4200045CUL) /**< \brief (CAN1) Interrupt Line Enable */
|
||||
#define REG_CAN1_GFC (*(RwReg *)0x42000480UL) /**< \brief (CAN1) Global Filter Configuration */
|
||||
#define REG_CAN1_SIDFC (*(RwReg *)0x42000484UL) /**< \brief (CAN1) Standard ID Filter Configuration */
|
||||
#define REG_CAN1_XIDFC (*(RwReg *)0x42000488UL) /**< \brief (CAN1) Extended ID Filter Configuration */
|
||||
#define REG_CAN1_XIDAM (*(RwReg *)0x42000490UL) /**< \brief (CAN1) Extended ID AND Mask */
|
||||
#define REG_CAN1_HPMS (*(RoReg *)0x42000494UL) /**< \brief (CAN1) High Priority Message Status */
|
||||
#define REG_CAN1_NDAT1 (*(RwReg *)0x42000498UL) /**< \brief (CAN1) New Data 1 */
|
||||
#define REG_CAN1_NDAT2 (*(RwReg *)0x4200049CUL) /**< \brief (CAN1) New Data 2 */
|
||||
#define REG_CAN1_RXF0C (*(RwReg *)0x420004A0UL) /**< \brief (CAN1) Rx FIFO 0 Configuration */
|
||||
#define REG_CAN1_RXF0S (*(RoReg *)0x420004A4UL) /**< \brief (CAN1) Rx FIFO 0 Status */
|
||||
#define REG_CAN1_RXF0A (*(RwReg *)0x420004A8UL) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
|
||||
#define REG_CAN1_RXBC (*(RwReg *)0x420004ACUL) /**< \brief (CAN1) Rx Buffer Configuration */
|
||||
#define REG_CAN1_RXF1C (*(RwReg *)0x420004B0UL) /**< \brief (CAN1) Rx FIFO 1 Configuration */
|
||||
#define REG_CAN1_RXF1S (*(RoReg *)0x420004B4UL) /**< \brief (CAN1) Rx FIFO 1 Status */
|
||||
#define REG_CAN1_RXF1A (*(RwReg *)0x420004B8UL) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
|
||||
#define REG_CAN1_RXESC (*(RwReg *)0x420004BCUL) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
|
||||
#define REG_CAN1_TXBC (*(RwReg *)0x420004C0UL) /**< \brief (CAN1) Tx Buffer Configuration */
|
||||
#define REG_CAN1_TXFQS (*(RoReg *)0x420004C4UL) /**< \brief (CAN1) Tx FIFO / Queue Status */
|
||||
#define REG_CAN1_TXESC (*(RwReg *)0x420004C8UL) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
|
||||
#define REG_CAN1_TXBRP (*(RoReg *)0x420004CCUL) /**< \brief (CAN1) Tx Buffer Request Pending */
|
||||
#define REG_CAN1_TXBAR (*(RwReg *)0x420004D0UL) /**< \brief (CAN1) Tx Buffer Add Request */
|
||||
#define REG_CAN1_TXBCR (*(RwReg *)0x420004D4UL) /**< \brief (CAN1) Tx Buffer Cancellation Request */
|
||||
#define REG_CAN1_TXBTO (*(RoReg *)0x420004D8UL) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
|
||||
#define REG_CAN1_TXBCF (*(RoReg *)0x420004DCUL) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
|
||||
#define REG_CAN1_TXBTIE (*(RwReg *)0x420004E0UL) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
|
||||
#define REG_CAN1_TXBCIE (*(RwReg *)0x420004E4UL) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
|
||||
#define REG_CAN1_TXEFC (*(RwReg *)0x420004F0UL) /**< \brief (CAN1) Tx Event FIFO Configuration */
|
||||
#define REG_CAN1_TXEFS (*(RoReg *)0x420004F4UL) /**< \brief (CAN1) Tx Event FIFO Status */
|
||||
#define REG_CAN1_TXEFA (*(RwReg *)0x420004F8UL) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for CAN1 peripheral ========== */
|
||||
#define CAN1_CLK_AHB_ID 18 // Index of AHB clock
|
||||
#define CAN1_DMAC_ID_DEBUG 21 // DMA CAN Debug Req
|
||||
#define CAN1_GCLK_ID 28 // Index of Generic Clock
|
||||
#define CAN1_MSG_RAM_ADDR 0x20000000
|
||||
#define CAN1_QOS_RESET_VAL 1 // QOS reset value
|
||||
|
||||
#endif /* _SAME54_CAN1_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for CCL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CCL_INSTANCE_
|
||||
#define _SAMD51_CCL_INSTANCE_
|
||||
#ifndef _SAME54_CCL_INSTANCE_
|
||||
#define _SAME54_CCL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for CCL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -54,4 +54,4 @@
|
|||
#define CCL_LUT_NUM 4 // Number of LUT in a CCL
|
||||
#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL
|
||||
|
||||
#endif /* _SAMD51_CCL_INSTANCE_ */
|
||||
#endif /* _SAME54_CCL_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for CMCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CMCC_INSTANCE_
|
||||
#define _SAMD51_CMCC_INSTANCE_
|
||||
#ifndef _SAME54_CMCC_INSTANCE_
|
||||
#define _SAME54_CMCC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for CMCC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -58,4 +58,4 @@
|
|||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
|
||||
#endif /* _SAMD51_CMCC_INSTANCE_ */
|
||||
#endif /* _SAME54_CMCC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for DAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_DAC_INSTANCE_
|
||||
#define _SAMD51_DAC_INSTANCE_
|
||||
#ifndef _SAME54_DAC_INSTANCE_
|
||||
#define _SAME54_DAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -85,4 +85,4 @@
|
|||
#define DAC_GCLK_ID 42 // Index of Generic Clock
|
||||
#define DAC_STEP 7 // Number of steps to reach full scale
|
||||
|
||||
#endif /* _SAMD51_DAC_INSTANCE_ */
|
||||
#endif /* _SAME54_DAC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for DMAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_DMAC_INSTANCE_
|
||||
#define _SAMD51_DMAC_INSTANCE_
|
||||
#ifndef _SAME54_DMAC_INSTANCE_
|
||||
#define _SAME54_DMAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DMAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -593,4 +593,4 @@
|
|||
#define DMAC_TRIG_BITS 7 // Number of bits to select trigger source
|
||||
#define DMAC_TRIG_NUM 85 // Number of peripheral triggers
|
||||
|
||||
#endif /* _SAMD51_DMAC_INSTANCE_ */
|
||||
#endif /* _SAME54_DMAC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for DSU
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_DSU_INSTANCE_
|
||||
#define _SAMD51_DSU_INSTANCE_
|
||||
#ifndef _SAME54_DSU_INSTANCE_
|
||||
#define _SAME54_DSU_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DSU peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -42,8 +42,6 @@
|
|||
#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_CFG (0x4100201C) /**< \brief (DSU) Configuration */
|
||||
#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */
|
||||
#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */
|
||||
#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
|
||||
|
|
@ -71,8 +69,6 @@
|
|||
#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_CFG (*(RwReg *)0x4100201CUL) /**< \brief (DSU) Configuration */
|
||||
#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */
|
||||
#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */
|
||||
#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
|
||||
|
|
@ -96,4 +92,4 @@
|
|||
#define DSU_DMAC_ID_DCC0 2 // DMAC ID for DCC0 register
|
||||
#define DSU_DMAC_ID_DCC1 3 // DMAC ID for DCC1 register
|
||||
|
||||
#endif /* _SAMD51_DSU_INSTANCE_ */
|
||||
#endif /* _SAME54_DSU_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for EIC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_EIC_INSTANCE_
|
||||
#define _SAMD51_EIC_INSTANCE_
|
||||
#ifndef _SAME54_EIC_INSTANCE_
|
||||
#define _SAME54_EIC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EIC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -70,4 +70,4 @@
|
|||
#define EIC_NUMBER_OF_DPRESCALER_REGS 2 // Number of DPRESCALER pin groups
|
||||
#define EIC_NUMBER_OF_INTERRUPTS 16 // Number of external interrupts (obsolete)
|
||||
|
||||
#endif /* _SAMD51_EIC_INSTANCE_ */
|
||||
#endif /* _SAME54_EIC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_EVSYS_INSTANCE_
|
||||
#define _SAMD51_EVSYS_INSTANCE_
|
||||
#ifndef _SAME54_EVSYS_INSTANCE_
|
||||
#define _SAME54_EVSYS_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EVSYS peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -572,65 +572,65 @@
|
|||
#define EVSYS_ID_GEN_TCC0_OVF 41
|
||||
#define EVSYS_ID_GEN_TCC0_TRG 42
|
||||
#define EVSYS_ID_GEN_TCC0_CNT 43
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_0 44
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_1 45
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_2 46
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_3 47
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_4 48
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_5 49
|
||||
#define EVSYS_ID_GEN_TCC0_MC_0 44
|
||||
#define EVSYS_ID_GEN_TCC0_MC_1 45
|
||||
#define EVSYS_ID_GEN_TCC0_MC_2 46
|
||||
#define EVSYS_ID_GEN_TCC0_MC_3 47
|
||||
#define EVSYS_ID_GEN_TCC0_MC_4 48
|
||||
#define EVSYS_ID_GEN_TCC0_MC_5 49
|
||||
#define EVSYS_ID_GEN_TCC1_OVF 50
|
||||
#define EVSYS_ID_GEN_TCC1_TRG 51
|
||||
#define EVSYS_ID_GEN_TCC1_CNT 52
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_0 53
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_1 54
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_2 55
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_3 56
|
||||
#define EVSYS_ID_GEN_TCC1_MC_0 53
|
||||
#define EVSYS_ID_GEN_TCC1_MC_1 54
|
||||
#define EVSYS_ID_GEN_TCC1_MC_2 55
|
||||
#define EVSYS_ID_GEN_TCC1_MC_3 56
|
||||
#define EVSYS_ID_GEN_TCC2_OVF 57
|
||||
#define EVSYS_ID_GEN_TCC2_TRG 58
|
||||
#define EVSYS_ID_GEN_TCC2_CNT 59
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_0 60
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_1 61
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_2 62
|
||||
#define EVSYS_ID_GEN_TCC2_MC_0 60
|
||||
#define EVSYS_ID_GEN_TCC2_MC_1 61
|
||||
#define EVSYS_ID_GEN_TCC2_MC_2 62
|
||||
#define EVSYS_ID_GEN_TCC3_OVF 63
|
||||
#define EVSYS_ID_GEN_TCC3_TRG 64
|
||||
#define EVSYS_ID_GEN_TCC3_CNT 65
|
||||
#define EVSYS_ID_GEN_TCC3_MCX_0 66
|
||||
#define EVSYS_ID_GEN_TCC3_MCX_1 67
|
||||
#define EVSYS_ID_GEN_TCC3_MC_0 66
|
||||
#define EVSYS_ID_GEN_TCC3_MC_1 67
|
||||
#define EVSYS_ID_GEN_TCC4_OVF 68
|
||||
#define EVSYS_ID_GEN_TCC4_TRG 69
|
||||
#define EVSYS_ID_GEN_TCC4_CNT 70
|
||||
#define EVSYS_ID_GEN_TCC4_MCX_0 71
|
||||
#define EVSYS_ID_GEN_TCC4_MCX_1 72
|
||||
#define EVSYS_ID_GEN_TCC4_MC_0 71
|
||||
#define EVSYS_ID_GEN_TCC4_MC_1 72
|
||||
#define EVSYS_ID_GEN_TC0_OVF 73
|
||||
#define EVSYS_ID_GEN_TC0_MCX_0 74
|
||||
#define EVSYS_ID_GEN_TC0_MCX_1 75
|
||||
#define EVSYS_ID_GEN_TC0_MC_0 74
|
||||
#define EVSYS_ID_GEN_TC0_MC_1 75
|
||||
#define EVSYS_ID_GEN_TC1_OVF 76
|
||||
#define EVSYS_ID_GEN_TC1_MCX_0 77
|
||||
#define EVSYS_ID_GEN_TC1_MCX_1 78
|
||||
#define EVSYS_ID_GEN_TC1_MC_0 77
|
||||
#define EVSYS_ID_GEN_TC1_MC_1 78
|
||||
#define EVSYS_ID_GEN_TC2_OVF 79
|
||||
#define EVSYS_ID_GEN_TC2_MCX_0 80
|
||||
#define EVSYS_ID_GEN_TC2_MCX_1 81
|
||||
#define EVSYS_ID_GEN_TC2_MC_0 80
|
||||
#define EVSYS_ID_GEN_TC2_MC_1 81
|
||||
#define EVSYS_ID_GEN_TC3_OVF 82
|
||||
#define EVSYS_ID_GEN_TC3_MCX_0 83
|
||||
#define EVSYS_ID_GEN_TC3_MCX_1 84
|
||||
#define EVSYS_ID_GEN_TC3_MC_0 83
|
||||
#define EVSYS_ID_GEN_TC3_MC_1 84
|
||||
#define EVSYS_ID_GEN_TC4_OVF 85
|
||||
#define EVSYS_ID_GEN_TC4_MCX_0 86
|
||||
#define EVSYS_ID_GEN_TC4_MCX_1 87
|
||||
#define EVSYS_ID_GEN_TC4_MC_0 86
|
||||
#define EVSYS_ID_GEN_TC4_MC_1 87
|
||||
#define EVSYS_ID_GEN_TC5_OVF 88
|
||||
#define EVSYS_ID_GEN_TC5_MCX_0 89
|
||||
#define EVSYS_ID_GEN_TC5_MCX_1 90
|
||||
#define EVSYS_ID_GEN_TC5_MC_0 89
|
||||
#define EVSYS_ID_GEN_TC5_MC_1 90
|
||||
#define EVSYS_ID_GEN_TC6_OVF 91
|
||||
#define EVSYS_ID_GEN_TC6_MCX_0 92
|
||||
#define EVSYS_ID_GEN_TC6_MCX_1 93
|
||||
#define EVSYS_ID_GEN_TC6_MC_0 92
|
||||
#define EVSYS_ID_GEN_TC6_MC_1 93
|
||||
#define EVSYS_ID_GEN_TC7_OVF 94
|
||||
#define EVSYS_ID_GEN_TC7_MCX_0 95
|
||||
#define EVSYS_ID_GEN_TC7_MCX_1 96
|
||||
#define EVSYS_ID_GEN_TC7_MC_0 95
|
||||
#define EVSYS_ID_GEN_TC7_MC_1 96
|
||||
#define EVSYS_ID_GEN_PDEC_OVF 97
|
||||
#define EVSYS_ID_GEN_PDEC_ERR 98
|
||||
#define EVSYS_ID_GEN_PDEC_DIR 99
|
||||
#define EVSYS_ID_GEN_PDEC_VLC 100
|
||||
#define EVSYS_ID_GEN_PDEC_MCX_0 101
|
||||
#define EVSYS_ID_GEN_PDEC_MCX_1 102
|
||||
#define EVSYS_ID_GEN_PDEC_MC_0 101
|
||||
#define EVSYS_ID_GEN_PDEC_MC_1 102
|
||||
#define EVSYS_ID_GEN_ADC0_RESRDY 103
|
||||
#define EVSYS_ID_GEN_ADC0_WINMON 104
|
||||
#define EVSYS_ID_GEN_ADC1_RESRDY 105
|
||||
|
|
@ -642,6 +642,7 @@
|
|||
#define EVSYS_ID_GEN_DAC_EMPTY_1 111
|
||||
#define EVSYS_ID_GEN_DAC_RESRDY_0 112
|
||||
#define EVSYS_ID_GEN_DAC_RESRDY_1 113
|
||||
#define EVSYS_ID_GEN_GMAC_TSU_CMP 114
|
||||
#define EVSYS_ID_GEN_TRNG_READY 115
|
||||
#define EVSYS_ID_GEN_CCL_LUTOUT_0 116
|
||||
#define EVSYS_ID_GEN_CCL_LUTOUT_1 117
|
||||
|
|
@ -716,4 +717,4 @@
|
|||
#define EVSYS_ID_USER_CCL_LUTIN_2 65
|
||||
#define EVSYS_ID_USER_CCL_LUTIN_3 66
|
||||
|
||||
#endif /* _SAMD51_EVSYS_INSTANCE_ */
|
||||
#endif /* _SAME54_EVSYS_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for FREQM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_FREQM_INSTANCE_
|
||||
#define _SAMD51_FREQM_INSTANCE_
|
||||
#ifndef _SAME54_FREQM_INSTANCE_
|
||||
#define _SAME54_FREQM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for FREQM peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -56,4 +56,4 @@
|
|||
/* ========== Instance parameters for FREQM peripheral ========== */
|
||||
#define FREQM_GCLK_ID_MSR 5 // Index of measure generic clock
|
||||
|
||||
#endif /* _SAMD51_FREQM_INSTANCE_ */
|
||||
#endif /* _SAME54_FREQM_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for GCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_GCLK_INSTANCE_
|
||||
#define _SAMD51_GCLK_INSTANCE_
|
||||
#ifndef _SAME54_GCLK_INSTANCE_
|
||||
#define _SAME54_GCLK_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GCLK peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -188,4 +188,4 @@
|
|||
#define GCLK_SOURCE_FDPLL1 8 // Alias to GCLK_SOURCE_DPLL1
|
||||
#define GCLK_GEN_DIV_BITS { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }
|
||||
|
||||
#endif /* _SAMD51_GCLK_INSTANCE_ */
|
||||
#endif /* _SAME54_GCLK_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for GMAC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAME54_GMAC_INSTANCE_
|
||||
#define _SAME54_GMAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GMAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_GMAC_NCR (0x42000800) /**< \brief (GMAC) Network Control Register */
|
||||
#define REG_GMAC_NCFGR (0x42000804) /**< \brief (GMAC) Network Configuration Register */
|
||||
#define REG_GMAC_NSR (0x42000808) /**< \brief (GMAC) Network Status Register */
|
||||
#define REG_GMAC_UR (0x4200080C) /**< \brief (GMAC) User Register */
|
||||
#define REG_GMAC_DCFGR (0x42000810) /**< \brief (GMAC) DMA Configuration Register */
|
||||
#define REG_GMAC_TSR (0x42000814) /**< \brief (GMAC) Transmit Status Register */
|
||||
#define REG_GMAC_RBQB (0x42000818) /**< \brief (GMAC) Receive Buffer Queue Base Address */
|
||||
#define REG_GMAC_TBQB (0x4200081C) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
|
||||
#define REG_GMAC_RSR (0x42000820) /**< \brief (GMAC) Receive Status Register */
|
||||
#define REG_GMAC_ISR (0x42000824) /**< \brief (GMAC) Interrupt Status Register */
|
||||
#define REG_GMAC_IER (0x42000828) /**< \brief (GMAC) Interrupt Enable Register */
|
||||
#define REG_GMAC_IDR (0x4200082C) /**< \brief (GMAC) Interrupt Disable Register */
|
||||
#define REG_GMAC_IMR (0x42000830) /**< \brief (GMAC) Interrupt Mask Register */
|
||||
#define REG_GMAC_MAN (0x42000834) /**< \brief (GMAC) PHY Maintenance Register */
|
||||
#define REG_GMAC_RPQ (0x42000838) /**< \brief (GMAC) Received Pause Quantum Register */
|
||||
#define REG_GMAC_TPQ (0x4200083C) /**< \brief (GMAC) Transmit Pause Quantum Register */
|
||||
#define REG_GMAC_TPSF (0x42000840) /**< \brief (GMAC) TX partial store and forward Register */
|
||||
#define REG_GMAC_RPSF (0x42000844) /**< \brief (GMAC) RX partial store and forward Register */
|
||||
#define REG_GMAC_RJFML (0x42000848) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
|
||||
#define REG_GMAC_HRB (0x42000880) /**< \brief (GMAC) Hash Register Bottom [31:0] */
|
||||
#define REG_GMAC_HRT (0x42000884) /**< \brief (GMAC) Hash Register Top [63:32] */
|
||||
#define REG_GMAC_SAB0 (0x42000888) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 0 */
|
||||
#define REG_GMAC_SAT0 (0x4200088C) /**< \brief (GMAC) Specific Address Top [47:32] Register 0 */
|
||||
#define REG_GMAC_SAB1 (0x42000890) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 1 */
|
||||
#define REG_GMAC_SAT1 (0x42000894) /**< \brief (GMAC) Specific Address Top [47:32] Register 1 */
|
||||
#define REG_GMAC_SAB2 (0x42000898) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 2 */
|
||||
#define REG_GMAC_SAT2 (0x4200089C) /**< \brief (GMAC) Specific Address Top [47:32] Register 2 */
|
||||
#define REG_GMAC_SAB3 (0x420008A0) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 3 */
|
||||
#define REG_GMAC_SAT3 (0x420008A4) /**< \brief (GMAC) Specific Address Top [47:32] Register 3 */
|
||||
#define REG_GMAC_TIDM0 (0x420008A8) /**< \brief (GMAC) Type ID Match Register 0 */
|
||||
#define REG_GMAC_TIDM1 (0x420008AC) /**< \brief (GMAC) Type ID Match Register 1 */
|
||||
#define REG_GMAC_TIDM2 (0x420008B0) /**< \brief (GMAC) Type ID Match Register 2 */
|
||||
#define REG_GMAC_TIDM3 (0x420008B4) /**< \brief (GMAC) Type ID Match Register 3 */
|
||||
#define REG_GMAC_WOL (0x420008B8) /**< \brief (GMAC) Wake on LAN */
|
||||
#define REG_GMAC_IPGS (0x420008BC) /**< \brief (GMAC) IPG Stretch Register */
|
||||
#define REG_GMAC_SVLAN (0x420008C0) /**< \brief (GMAC) Stacked VLAN Register */
|
||||
#define REG_GMAC_TPFCP (0x420008C4) /**< \brief (GMAC) Transmit PFC Pause Register */
|
||||
#define REG_GMAC_SAMB1 (0x420008C8) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
|
||||
#define REG_GMAC_SAMT1 (0x420008CC) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
|
||||
#define REG_GMAC_NSC (0x420008DC) /**< \brief (GMAC) Tsu timer comparison nanoseconds Register */
|
||||
#define REG_GMAC_SCL (0x420008E0) /**< \brief (GMAC) Tsu timer second comparison Register */
|
||||
#define REG_GMAC_SCH (0x420008E4) /**< \brief (GMAC) Tsu timer second comparison Register */
|
||||
#define REG_GMAC_EFTSH (0x420008E8) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_EFRSH (0x420008EC) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_PEFTSH (0x420008F0) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_PEFRSH (0x420008F4) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_OTLO (0x42000900) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
|
||||
#define REG_GMAC_OTHI (0x42000904) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
|
||||
#define REG_GMAC_FT (0x42000908) /**< \brief (GMAC) Frames Transmitted Register */
|
||||
#define REG_GMAC_BCFT (0x4200090C) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
|
||||
#define REG_GMAC_MFT (0x42000910) /**< \brief (GMAC) Multicast Frames Transmitted Register */
|
||||
#define REG_GMAC_PFT (0x42000914) /**< \brief (GMAC) Pause Frames Transmitted Register */
|
||||
#define REG_GMAC_BFT64 (0x42000918) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT127 (0x4200091C) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT255 (0x42000920) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT511 (0x42000924) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1023 (0x42000928) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1518 (0x4200092C) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_GTBFT1518 (0x42000930) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TUR (0x42000934) /**< \brief (GMAC) Transmit Underruns Register */
|
||||
#define REG_GMAC_SCF (0x42000938) /**< \brief (GMAC) Single Collision Frames Register */
|
||||
#define REG_GMAC_MCF (0x4200093C) /**< \brief (GMAC) Multiple Collision Frames Register */
|
||||
#define REG_GMAC_EC (0x42000940) /**< \brief (GMAC) Excessive Collisions Register */
|
||||
#define REG_GMAC_LC (0x42000944) /**< \brief (GMAC) Late Collisions Register */
|
||||
#define REG_GMAC_DTF (0x42000948) /**< \brief (GMAC) Deferred Transmission Frames Register */
|
||||
#define REG_GMAC_CSE (0x4200094C) /**< \brief (GMAC) Carrier Sense Errors Register */
|
||||
#define REG_GMAC_ORLO (0x42000950) /**< \brief (GMAC) Octets Received [31:0] Received */
|
||||
#define REG_GMAC_ORHI (0x42000954) /**< \brief (GMAC) Octets Received [47:32] Received */
|
||||
#define REG_GMAC_FR (0x42000958) /**< \brief (GMAC) Frames Received Register */
|
||||
#define REG_GMAC_BCFR (0x4200095C) /**< \brief (GMAC) Broadcast Frames Received Register */
|
||||
#define REG_GMAC_MFR (0x42000960) /**< \brief (GMAC) Multicast Frames Received Register */
|
||||
#define REG_GMAC_PFR (0x42000964) /**< \brief (GMAC) Pause Frames Received Register */
|
||||
#define REG_GMAC_BFR64 (0x42000968) /**< \brief (GMAC) 64 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR127 (0x4200096C) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR255 (0x42000970) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR511 (0x42000974) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1023 (0x42000978) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1518 (0x4200097C) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
|
||||
#define REG_GMAC_TMXBFR (0x42000980) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
|
||||
#define REG_GMAC_UFR (0x42000984) /**< \brief (GMAC) Undersize Frames Received Register */
|
||||
#define REG_GMAC_OFR (0x42000988) /**< \brief (GMAC) Oversize Frames Received Register */
|
||||
#define REG_GMAC_JR (0x4200098C) /**< \brief (GMAC) Jabbers Received Register */
|
||||
#define REG_GMAC_FCSE (0x42000990) /**< \brief (GMAC) Frame Check Sequence Errors Register */
|
||||
#define REG_GMAC_LFFE (0x42000994) /**< \brief (GMAC) Length Field Frame Errors Register */
|
||||
#define REG_GMAC_RSE (0x42000998) /**< \brief (GMAC) Receive Symbol Errors Register */
|
||||
#define REG_GMAC_AE (0x4200099C) /**< \brief (GMAC) Alignment Errors Register */
|
||||
#define REG_GMAC_RRE (0x420009A0) /**< \brief (GMAC) Receive Resource Errors Register */
|
||||
#define REG_GMAC_ROE (0x420009A4) /**< \brief (GMAC) Receive Overrun Register */
|
||||
#define REG_GMAC_IHCE (0x420009A8) /**< \brief (GMAC) IP Header Checksum Errors Register */
|
||||
#define REG_GMAC_TCE (0x420009AC) /**< \brief (GMAC) TCP Checksum Errors Register */
|
||||
#define REG_GMAC_UCE (0x420009B0) /**< \brief (GMAC) UDP Checksum Errors Register */
|
||||
#define REG_GMAC_TISUBN (0x420009BC) /**< \brief (GMAC) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
|
||||
#define REG_GMAC_TSH (0x420009C0) /**< \brief (GMAC) 1588 Timer Seconds High [15:0] Register */
|
||||
#define REG_GMAC_TSSSL (0x420009C8) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds [31:0] Register */
|
||||
#define REG_GMAC_TSSN (0x420009CC) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
|
||||
#define REG_GMAC_TSL (0x420009D0) /**< \brief (GMAC) 1588 Timer Seconds [31:0] Register */
|
||||
#define REG_GMAC_TN (0x420009D4) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
|
||||
#define REG_GMAC_TA (0x420009D8) /**< \brief (GMAC) 1588 Timer Adjust Register */
|
||||
#define REG_GMAC_TI (0x420009DC) /**< \brief (GMAC) 1588 Timer Increment Register */
|
||||
#define REG_GMAC_EFTSL (0x420009E0) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_EFTN (0x420009E4) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
|
||||
#define REG_GMAC_EFRSL (0x420009E8) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_EFRN (0x420009EC) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
|
||||
#define REG_GMAC_PEFTSL (0x420009F0) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_PEFTN (0x420009F4) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
|
||||
#define REG_GMAC_PEFRSL (0x420009F8) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_PEFRN (0x420009FC) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
|
||||
#define REG_GMAC_RLPITR (0x42000A70) /**< \brief (GMAC) Receive LPI transition Register */
|
||||
#define REG_GMAC_RLPITI (0x42000A74) /**< \brief (GMAC) Receive LPI Time Register */
|
||||
#define REG_GMAC_TLPITR (0x42000A78) /**< \brief (GMAC) Receive LPI transition Register */
|
||||
#define REG_GMAC_TLPITI (0x42000A7C) /**< \brief (GMAC) Receive LPI Time Register */
|
||||
#else
|
||||
#define REG_GMAC_NCR (*(RwReg *)0x42000800UL) /**< \brief (GMAC) Network Control Register */
|
||||
#define REG_GMAC_NCFGR (*(RwReg *)0x42000804UL) /**< \brief (GMAC) Network Configuration Register */
|
||||
#define REG_GMAC_NSR (*(RoReg *)0x42000808UL) /**< \brief (GMAC) Network Status Register */
|
||||
#define REG_GMAC_UR (*(RwReg *)0x4200080CUL) /**< \brief (GMAC) User Register */
|
||||
#define REG_GMAC_DCFGR (*(RwReg *)0x42000810UL) /**< \brief (GMAC) DMA Configuration Register */
|
||||
#define REG_GMAC_TSR (*(RwReg *)0x42000814UL) /**< \brief (GMAC) Transmit Status Register */
|
||||
#define REG_GMAC_RBQB (*(RwReg *)0x42000818UL) /**< \brief (GMAC) Receive Buffer Queue Base Address */
|
||||
#define REG_GMAC_TBQB (*(RwReg *)0x4200081CUL) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
|
||||
#define REG_GMAC_RSR (*(RwReg *)0x42000820UL) /**< \brief (GMAC) Receive Status Register */
|
||||
#define REG_GMAC_ISR (*(RwReg *)0x42000824UL) /**< \brief (GMAC) Interrupt Status Register */
|
||||
#define REG_GMAC_IER (*(WoReg *)0x42000828UL) /**< \brief (GMAC) Interrupt Enable Register */
|
||||
#define REG_GMAC_IDR (*(WoReg *)0x4200082CUL) /**< \brief (GMAC) Interrupt Disable Register */
|
||||
#define REG_GMAC_IMR (*(RoReg *)0x42000830UL) /**< \brief (GMAC) Interrupt Mask Register */
|
||||
#define REG_GMAC_MAN (*(RwReg *)0x42000834UL) /**< \brief (GMAC) PHY Maintenance Register */
|
||||
#define REG_GMAC_RPQ (*(RoReg *)0x42000838UL) /**< \brief (GMAC) Received Pause Quantum Register */
|
||||
#define REG_GMAC_TPQ (*(RwReg *)0x4200083CUL) /**< \brief (GMAC) Transmit Pause Quantum Register */
|
||||
#define REG_GMAC_TPSF (*(RwReg *)0x42000840UL) /**< \brief (GMAC) TX partial store and forward Register */
|
||||
#define REG_GMAC_RPSF (*(RwReg *)0x42000844UL) /**< \brief (GMAC) RX partial store and forward Register */
|
||||
#define REG_GMAC_RJFML (*(RwReg *)0x42000848UL) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
|
||||
#define REG_GMAC_HRB (*(RwReg *)0x42000880UL) /**< \brief (GMAC) Hash Register Bottom [31:0] */
|
||||
#define REG_GMAC_HRT (*(RwReg *)0x42000884UL) /**< \brief (GMAC) Hash Register Top [63:32] */
|
||||
#define REG_GMAC_SAB0 (*(RwReg *)0x42000888UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 0 */
|
||||
#define REG_GMAC_SAT0 (*(RwReg *)0x4200088CUL) /**< \brief (GMAC) Specific Address Top [47:32] Register 0 */
|
||||
#define REG_GMAC_SAB1 (*(RwReg *)0x42000890UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 1 */
|
||||
#define REG_GMAC_SAT1 (*(RwReg *)0x42000894UL) /**< \brief (GMAC) Specific Address Top [47:32] Register 1 */
|
||||
#define REG_GMAC_SAB2 (*(RwReg *)0x42000898UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 2 */
|
||||
#define REG_GMAC_SAT2 (*(RwReg *)0x4200089CUL) /**< \brief (GMAC) Specific Address Top [47:32] Register 2 */
|
||||
#define REG_GMAC_SAB3 (*(RwReg *)0x420008A0UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 3 */
|
||||
#define REG_GMAC_SAT3 (*(RwReg *)0x420008A4UL) /**< \brief (GMAC) Specific Address Top [47:32] Register 3 */
|
||||
#define REG_GMAC_TIDM0 (*(RwReg *)0x420008A8UL) /**< \brief (GMAC) Type ID Match Register 0 */
|
||||
#define REG_GMAC_TIDM1 (*(RwReg *)0x420008ACUL) /**< \brief (GMAC) Type ID Match Register 1 */
|
||||
#define REG_GMAC_TIDM2 (*(RwReg *)0x420008B0UL) /**< \brief (GMAC) Type ID Match Register 2 */
|
||||
#define REG_GMAC_TIDM3 (*(RwReg *)0x420008B4UL) /**< \brief (GMAC) Type ID Match Register 3 */
|
||||
#define REG_GMAC_WOL (*(RwReg *)0x420008B8UL) /**< \brief (GMAC) Wake on LAN */
|
||||
#define REG_GMAC_IPGS (*(RwReg *)0x420008BCUL) /**< \brief (GMAC) IPG Stretch Register */
|
||||
#define REG_GMAC_SVLAN (*(RwReg *)0x420008C0UL) /**< \brief (GMAC) Stacked VLAN Register */
|
||||
#define REG_GMAC_TPFCP (*(RwReg *)0x420008C4UL) /**< \brief (GMAC) Transmit PFC Pause Register */
|
||||
#define REG_GMAC_SAMB1 (*(RwReg *)0x420008C8UL) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
|
||||
#define REG_GMAC_SAMT1 (*(RwReg *)0x420008CCUL) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
|
||||
#define REG_GMAC_NSC (*(RwReg *)0x420008DCUL) /**< \brief (GMAC) Tsu timer comparison nanoseconds Register */
|
||||
#define REG_GMAC_SCL (*(RwReg *)0x420008E0UL) /**< \brief (GMAC) Tsu timer second comparison Register */
|
||||
#define REG_GMAC_SCH (*(RwReg *)0x420008E4UL) /**< \brief (GMAC) Tsu timer second comparison Register */
|
||||
#define REG_GMAC_EFTSH (*(RoReg *)0x420008E8UL) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_EFRSH (*(RoReg *)0x420008ECUL) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_PEFTSH (*(RoReg *)0x420008F0UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_PEFRSH (*(RoReg *)0x420008F4UL) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_OTLO (*(RoReg *)0x42000900UL) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
|
||||
#define REG_GMAC_OTHI (*(RoReg *)0x42000904UL) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
|
||||
#define REG_GMAC_FT (*(RoReg *)0x42000908UL) /**< \brief (GMAC) Frames Transmitted Register */
|
||||
#define REG_GMAC_BCFT (*(RoReg *)0x4200090CUL) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
|
||||
#define REG_GMAC_MFT (*(RoReg *)0x42000910UL) /**< \brief (GMAC) Multicast Frames Transmitted Register */
|
||||
#define REG_GMAC_PFT (*(RoReg *)0x42000914UL) /**< \brief (GMAC) Pause Frames Transmitted Register */
|
||||
#define REG_GMAC_BFT64 (*(RoReg *)0x42000918UL) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT127 (*(RoReg *)0x4200091CUL) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT255 (*(RoReg *)0x42000920UL) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT511 (*(RoReg *)0x42000924UL) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1023 (*(RoReg *)0x42000928UL) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1518 (*(RoReg *)0x4200092CUL) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_GTBFT1518 (*(RoReg *)0x42000930UL) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TUR (*(RoReg *)0x42000934UL) /**< \brief (GMAC) Transmit Underruns Register */
|
||||
#define REG_GMAC_SCF (*(RoReg *)0x42000938UL) /**< \brief (GMAC) Single Collision Frames Register */
|
||||
#define REG_GMAC_MCF (*(RoReg *)0x4200093CUL) /**< \brief (GMAC) Multiple Collision Frames Register */
|
||||
#define REG_GMAC_EC (*(RoReg *)0x42000940UL) /**< \brief (GMAC) Excessive Collisions Register */
|
||||
#define REG_GMAC_LC (*(RoReg *)0x42000944UL) /**< \brief (GMAC) Late Collisions Register */
|
||||
#define REG_GMAC_DTF (*(RoReg *)0x42000948UL) /**< \brief (GMAC) Deferred Transmission Frames Register */
|
||||
#define REG_GMAC_CSE (*(RoReg *)0x4200094CUL) /**< \brief (GMAC) Carrier Sense Errors Register */
|
||||
#define REG_GMAC_ORLO (*(RoReg *)0x42000950UL) /**< \brief (GMAC) Octets Received [31:0] Received */
|
||||
#define REG_GMAC_ORHI (*(RoReg *)0x42000954UL) /**< \brief (GMAC) Octets Received [47:32] Received */
|
||||
#define REG_GMAC_FR (*(RoReg *)0x42000958UL) /**< \brief (GMAC) Frames Received Register */
|
||||
#define REG_GMAC_BCFR (*(RoReg *)0x4200095CUL) /**< \brief (GMAC) Broadcast Frames Received Register */
|
||||
#define REG_GMAC_MFR (*(RoReg *)0x42000960UL) /**< \brief (GMAC) Multicast Frames Received Register */
|
||||
#define REG_GMAC_PFR (*(RoReg *)0x42000964UL) /**< \brief (GMAC) Pause Frames Received Register */
|
||||
#define REG_GMAC_BFR64 (*(RoReg *)0x42000968UL) /**< \brief (GMAC) 64 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR127 (*(RoReg *)0x4200096CUL) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR255 (*(RoReg *)0x42000970UL) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR511 (*(RoReg *)0x42000974UL) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1023 (*(RoReg *)0x42000978UL) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1518 (*(RoReg *)0x4200097CUL) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
|
||||
#define REG_GMAC_TMXBFR (*(RoReg *)0x42000980UL) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
|
||||
#define REG_GMAC_UFR (*(RoReg *)0x42000984UL) /**< \brief (GMAC) Undersize Frames Received Register */
|
||||
#define REG_GMAC_OFR (*(RoReg *)0x42000988UL) /**< \brief (GMAC) Oversize Frames Received Register */
|
||||
#define REG_GMAC_JR (*(RoReg *)0x4200098CUL) /**< \brief (GMAC) Jabbers Received Register */
|
||||
#define REG_GMAC_FCSE (*(RoReg *)0x42000990UL) /**< \brief (GMAC) Frame Check Sequence Errors Register */
|
||||
#define REG_GMAC_LFFE (*(RoReg *)0x42000994UL) /**< \brief (GMAC) Length Field Frame Errors Register */
|
||||
#define REG_GMAC_RSE (*(RoReg *)0x42000998UL) /**< \brief (GMAC) Receive Symbol Errors Register */
|
||||
#define REG_GMAC_AE (*(RoReg *)0x4200099CUL) /**< \brief (GMAC) Alignment Errors Register */
|
||||
#define REG_GMAC_RRE (*(RoReg *)0x420009A0UL) /**< \brief (GMAC) Receive Resource Errors Register */
|
||||
#define REG_GMAC_ROE (*(RoReg *)0x420009A4UL) /**< \brief (GMAC) Receive Overrun Register */
|
||||
#define REG_GMAC_IHCE (*(RoReg *)0x420009A8UL) /**< \brief (GMAC) IP Header Checksum Errors Register */
|
||||
#define REG_GMAC_TCE (*(RoReg *)0x420009ACUL) /**< \brief (GMAC) TCP Checksum Errors Register */
|
||||
#define REG_GMAC_UCE (*(RoReg *)0x420009B0UL) /**< \brief (GMAC) UDP Checksum Errors Register */
|
||||
#define REG_GMAC_TISUBN (*(RwReg *)0x420009BCUL) /**< \brief (GMAC) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
|
||||
#define REG_GMAC_TSH (*(RwReg *)0x420009C0UL) /**< \brief (GMAC) 1588 Timer Seconds High [15:0] Register */
|
||||
#define REG_GMAC_TSSSL (*(RwReg *)0x420009C8UL) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds [31:0] Register */
|
||||
#define REG_GMAC_TSSN (*(RwReg *)0x420009CCUL) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
|
||||
#define REG_GMAC_TSL (*(RwReg *)0x420009D0UL) /**< \brief (GMAC) 1588 Timer Seconds [31:0] Register */
|
||||
#define REG_GMAC_TN (*(RwReg *)0x420009D4UL) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
|
||||
#define REG_GMAC_TA (*(WoReg *)0x420009D8UL) /**< \brief (GMAC) 1588 Timer Adjust Register */
|
||||
#define REG_GMAC_TI (*(RwReg *)0x420009DCUL) /**< \brief (GMAC) 1588 Timer Increment Register */
|
||||
#define REG_GMAC_EFTSL (*(RoReg *)0x420009E0UL) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_EFTN (*(RoReg *)0x420009E4UL) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
|
||||
#define REG_GMAC_EFRSL (*(RoReg *)0x420009E8UL) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_EFRN (*(RoReg *)0x420009ECUL) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
|
||||
#define REG_GMAC_PEFTSL (*(RoReg *)0x420009F0UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_PEFTN (*(RoReg *)0x420009F4UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
|
||||
#define REG_GMAC_PEFRSL (*(RoReg *)0x420009F8UL) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_PEFRN (*(RoReg *)0x420009FCUL) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
|
||||
#define REG_GMAC_RLPITR (*(RoReg *)0x42000A70UL) /**< \brief (GMAC) Receive LPI transition Register */
|
||||
#define REG_GMAC_RLPITI (*(RoReg *)0x42000A74UL) /**< \brief (GMAC) Receive LPI Time Register */
|
||||
#define REG_GMAC_TLPITR (*(RoReg *)0x42000A78UL) /**< \brief (GMAC) Receive LPI transition Register */
|
||||
#define REG_GMAC_TLPITI (*(RoReg *)0x42000A7CUL) /**< \brief (GMAC) Receive LPI Time Register */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for GMAC peripheral ========== */
|
||||
#define GMAC_CLK_AHB_ID 14 // Index of AHB clock
|
||||
|
||||
#endif /* _SAME54_GMAC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for HMATRIX
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_HMATRIX_INSTANCE_
|
||||
#define _SAMD51_HMATRIX_INSTANCE_
|
||||
#ifndef _SAME54_HMATRIX_INSTANCE_
|
||||
#define _SAME54_HMATRIX_INSTANCE_
|
||||
|
||||
/* ========== Register definition for HMATRIX peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -130,4 +130,4 @@
|
|||
#define HMATRIX_MASTER_DSU 7
|
||||
#define HMATRIX_MASTER_NUM 8
|
||||
|
||||
#endif /* _SAMD51_HMATRIX_INSTANCE_ */
|
||||
#endif /* _SAME54_HMATRIX_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for I2S
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_I2S_INSTANCE_
|
||||
#define _SAMD51_I2S_INSTANCE_
|
||||
#ifndef _SAME54_I2S_INSTANCE_
|
||||
#define _SAME54_I2S_INSTANCE_
|
||||
|
||||
/* ========== Register definition for I2S peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -78,4 +78,4 @@
|
|||
#define I2S_MAX_WL_BITS 32 // Max number of bits in data samples
|
||||
#define I2S_SER_NUM 2 // Number of serializers
|
||||
|
||||
#endif /* _SAMD51_I2S_INSTANCE_ */
|
||||
#endif /* _SAME54_I2S_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for ICM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_ICM_INSTANCE_
|
||||
#define _SAMD51_ICM_INSTANCE_
|
||||
#ifndef _SAME54_ICM_INSTANCE_
|
||||
#define _SAME54_ICM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ICM peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -74,4 +74,4 @@
|
|||
/* ========== Instance parameters for ICM peripheral ========== */
|
||||
#define ICM_CLK_AHB_ID 19
|
||||
|
||||
#endif /* _SAMD51_ICM_INSTANCE_ */
|
||||
#endif /* _SAME54_ICM_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for MCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_MCLK_INSTANCE_
|
||||
#define _SAMD51_MCLK_INSTANCE_
|
||||
#ifndef _SAME54_MCLK_INSTANCE_
|
||||
#define _SAME54_MCLK_INSTANCE_
|
||||
|
||||
/* ========== Register definition for MCLK peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -58,4 +58,4 @@
|
|||
/* ========== Instance parameters for MCLK peripheral ========== */
|
||||
#define MCLK_SYSTEM_CLOCK 48000000 // System Clock Frequency at Reset
|
||||
|
||||
#endif /* _SAMD51_MCLK_INSTANCE_ */
|
||||
#endif /* _SAME54_MCLK_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_NVMCTRL_INSTANCE_
|
||||
#define _SAMD51_NVMCTRL_INSTANCE_
|
||||
#ifndef _SAME54_NVMCTRL_INSTANCE_
|
||||
#define _SAME54_NVMCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for NVMCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -72,4 +72,4 @@
|
|||
#define NVMCTRL_CLK_AHB_ID_SMEEPROM 22 // Index of AHB Clock in PM.AHBMASK register for SMEE submodule
|
||||
#define NVMCTRL_PAGE_SIZE 512 // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array)
|
||||
|
||||
#endif /* _SAMD51_NVMCTRL_INSTANCE_ */
|
||||
#endif /* _SAME54_NVMCTRL_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for OSC32KCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_OSC32KCTRL_INSTANCE_
|
||||
#define _SAMD51_OSC32KCTRL_INSTANCE_
|
||||
#ifndef _SAME54_OSC32KCTRL_INSTANCE_
|
||||
#define _SAME54_OSC32KCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for OSC32KCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -56,4 +56,4 @@
|
|||
/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
|
||||
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 0 // OSC32K coarse calibration size
|
||||
|
||||
#endif /* _SAMD51_OSC32KCTRL_INSTANCE_ */
|
||||
#endif /* _SAME54_OSC32KCTRL_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for OSCCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_OSCCTRL_INSTANCE_
|
||||
#define _SAMD51_OSCCTRL_INSTANCE_
|
||||
#ifndef _SAME54_OSCCTRL_INSTANCE_
|
||||
#define _SAME54_OSCCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for OSCCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -127,4 +127,4 @@
|
|||
#define OSCCTRL_FDPLL_VERSION 0x100
|
||||
#define OSCCTRL_XOSC_VERSION 0x100
|
||||
|
||||
#endif /* _SAMD51_OSCCTRL_INSTANCE_ */
|
||||
#endif /* _SAME54_OSCCTRL_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PAC_INSTANCE_
|
||||
#define _SAMD51_PAC_INSTANCE_
|
||||
#ifndef _SAME54_PAC_INSTANCE_
|
||||
#define _SAME54_PAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -66,4 +66,4 @@
|
|||
#define PAC_CLK_AHB_ID 12 // AHB clock index
|
||||
#define PAC_HPB_NUM 4 // Number of bridges AHB/APB
|
||||
|
||||
#endif /* _SAMD51_PAC_INSTANCE_ */
|
||||
#endif /* _SAME54_PAC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PCC_INSTANCE_
|
||||
#define _SAMD51_PCC_INSTANCE_
|
||||
#ifndef _SAME54_PCC_INSTANCE_
|
||||
#define _SAME54_PCC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PCC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -55,4 +55,4 @@
|
|||
#define PCC_DATA_SIZE 14
|
||||
#define PCC_DMAC_ID_RX 80
|
||||
|
||||
#endif /* _SAMD51_PCC_INSTANCE_ */
|
||||
#endif /* _SAME54_PCC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PDEC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PDEC_INSTANCE_
|
||||
#define _SAMD51_PDEC_INSTANCE_
|
||||
#ifndef _SAME54_PDEC_INSTANCE_
|
||||
#define _SAME54_PDEC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PDEC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -77,4 +77,4 @@
|
|||
#define PDEC_CC_NUM 2 // Number of Compare Channels units
|
||||
#define PDEC_GCLK_ID 31
|
||||
|
||||
#endif /* _SAMD51_PDEC_INSTANCE_ */
|
||||
#endif /* _SAME54_PDEC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PM_INSTANCE_
|
||||
#define _SAMD51_PM_INSTANCE_
|
||||
#ifndef _SAME54_PM_INSTANCE_
|
||||
#define _SAME54_PM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PM peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -56,4 +56,4 @@
|
|||
/* ========== Instance parameters for PM peripheral ========== */
|
||||
#define PM_PD_NUM 0 // Number of switchable Power Domains
|
||||
|
||||
#endif /* _SAMD51_PM_INSTANCE_ */
|
||||
#endif /* _SAME54_PM_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PORT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PORT_INSTANCE_
|
||||
#define _SAMD51_PORT_INSTANCE_
|
||||
#ifndef _SAME54_PORT_INSTANCE_
|
||||
#define _SAME54_PORT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PORT peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -181,4 +181,4 @@
|
|||
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
|
||||
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
|
||||
|
||||
#endif /* _SAMD51_PORT_INSTANCE_ */
|
||||
#endif /* _SAME54_PORT_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PUKCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,12 +27,12 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_PUKCC_INSTANCE_
|
||||
#define _SAMD51_PUKCC_INSTANCE_
|
||||
#ifndef _SAME54_PUKCC_INSTANCE_
|
||||
#define _SAME54_PUKCC_INSTANCE_
|
||||
|
||||
/* ========== Instance parameters for PUKCC peripheral ========== */
|
||||
#define PUKCC_CLK_AHB_ID 20
|
||||
#define PUKCC_RAM_ADDR_SIZE 12
|
||||
#define PUKCC_ROM_ADDR_SIZE 16
|
||||
|
||||
#endif /* _SAMD51_PUKCC_INSTANCE_ */
|
||||
#endif /* _SAME54_PUKCC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for QSPI
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_QSPI_INSTANCE_
|
||||
#define _SAMD51_QSPI_INSTANCE_
|
||||
#ifndef _SAME54_QSPI_INSTANCE_
|
||||
#define _SAME54_QSPI_INSTANCE_
|
||||
|
||||
/* ========== Register definition for QSPI peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -69,4 +69,4 @@
|
|||
#define QSPI_HADDR_MSB 23
|
||||
#define QSPI_OCMS 1
|
||||
|
||||
#endif /* _SAMD51_QSPI_INSTANCE_ */
|
||||
#endif /* _SAME54_QSPI_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for RAMECC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_RAMECC_INSTANCE_
|
||||
#define _SAMD51_RAMECC_INSTANCE_
|
||||
#ifndef _SAME54_RAMECC_INSTANCE_
|
||||
#define _SAME54_RAMECC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RAMECC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -51,4 +51,4 @@
|
|||
#define RAMECC_RAMADDR_BITS 13 // Number of RAM address bits
|
||||
#define RAMECC_RAMBANK_NUM 4 // Number of RAM banks
|
||||
|
||||
#endif /* _SAMD51_RAMECC_INSTANCE_ */
|
||||
#endif /* _SAME54_RAMECC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for RSTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_RSTC_INSTANCE_
|
||||
#define _SAMD51_RSTC_INSTANCE_
|
||||
#ifndef _SAME54_RSTC_INSTANCE_
|
||||
#define _SAME54_RSTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RSTC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -45,4 +45,4 @@
|
|||
#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line
|
||||
#define RSTC_NVMRST_IMPLEMENTED 1
|
||||
|
||||
#endif /* _SAMD51_RSTC_INSTANCE_ */
|
||||
#endif /* _SAME54_RSTC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for RTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_RTC_INSTANCE_
|
||||
#define _SAMD51_RTC_INSTANCE_
|
||||
#ifndef _SAME54_RTC_INSTANCE_
|
||||
#define _SAME54_RTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -153,4 +153,4 @@
|
|||
#define RTC_NUM_OF_TAMPERS 5 // Number of Tamper Inputs
|
||||
#define RTC_PER_NUM 8 // Number of Periodic Intervals
|
||||
|
||||
#endif /* _SAMD51_RTC_INSTANCE_ */
|
||||
#endif /* _SAME54_RTC_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SDHC0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SDHC0_INSTANCE_
|
||||
#define _SAMD51_SDHC0_INSTANCE_
|
||||
#ifndef _SAME54_SDHC0_INSTANCE_
|
||||
#define _SAME54_SDHC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SDHC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -144,4 +144,4 @@
|
|||
#define SDHC0_NB_REG_PVR 8
|
||||
#define SDHC0_NB_REG_RR 4
|
||||
|
||||
#endif /* _SAMD51_SDHC0_INSTANCE_ */
|
||||
#endif /* _SAME54_SDHC0_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SDHC1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SDHC1_INSTANCE_
|
||||
#define _SAMD51_SDHC1_INSTANCE_
|
||||
#ifndef _SAME54_SDHC1_INSTANCE_
|
||||
#define _SAME54_SDHC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SDHC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -144,4 +144,4 @@
|
|||
#define SDHC1_NB_REG_PVR 8
|
||||
#define SDHC1_NB_REG_RR 4
|
||||
|
||||
#endif /* _SAMD51_SDHC1_INSTANCE_ */
|
||||
#endif /* _SAME54_SDHC1_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM0_INSTANCE_
|
||||
#define _SAMD51_SERCOM0_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM0_INSTANCE_
|
||||
#define _SAME54_SERCOM0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM0_GCLK_ID_CORE 7
|
||||
#define SERCOM0_GCLK_ID_SLOW 3
|
||||
#define SERCOM0_INT_MSB 6
|
||||
#define SERCOM0_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM0_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM0_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM0_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM0_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM0_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM0_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM0_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM0_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM0_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM0_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM0_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM0_PMSB 3
|
||||
#define SERCOM0_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM0_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM0_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM0_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM0_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM0_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM0_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM0_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM0_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM0_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM0_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM0_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM0_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM0_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM0_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM0_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM0_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM0_USART 1 // USART mode implemented?
|
||||
#define SERCOM0_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM0_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM0_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM0_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM0_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM0_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM1_INSTANCE_
|
||||
#define _SAMD51_SERCOM1_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM1_INSTANCE_
|
||||
#define _SAME54_SERCOM1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM1_GCLK_ID_CORE 8
|
||||
#define SERCOM1_GCLK_ID_SLOW 3
|
||||
#define SERCOM1_INT_MSB 6
|
||||
#define SERCOM1_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM1_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM1_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM1_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM1_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM1_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM1_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM1_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM1_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM1_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM1_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM1_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM1_PMSB 3
|
||||
#define SERCOM1_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM1_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM1_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM1_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM1_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM1_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM1_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM1_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM1_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM1_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM1_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM1_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM1_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM1_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM1_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM1_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM1_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM1_USART 1 // USART mode implemented?
|
||||
#define SERCOM1_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM1_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM1_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM1_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM1_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM1_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM2
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM2_INSTANCE_
|
||||
#define _SAMD51_SERCOM2_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM2_INSTANCE_
|
||||
#define _SAME54_SERCOM2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM2_GCLK_ID_CORE 23
|
||||
#define SERCOM2_GCLK_ID_SLOW 3
|
||||
#define SERCOM2_INT_MSB 6
|
||||
#define SERCOM2_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM2_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM2_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM2_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM2_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM2_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM2_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM2_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM2_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM2_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM2_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM2_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM2_PMSB 3
|
||||
#define SERCOM2_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM2_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM2_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM2_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM2_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM2_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM2_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM2_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM2_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM2_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM2_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM2_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM2_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM2_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM2_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM2_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM2_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM2_USART 1 // USART mode implemented?
|
||||
#define SERCOM2_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM2_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM2_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM2_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM2_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM2_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM3
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM3_INSTANCE_
|
||||
#define _SAMD51_SERCOM3_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM3_INSTANCE_
|
||||
#define _SAME54_SERCOM3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM3_GCLK_ID_CORE 24
|
||||
#define SERCOM3_GCLK_ID_SLOW 3
|
||||
#define SERCOM3_INT_MSB 6
|
||||
#define SERCOM3_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM3_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM3_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM3_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM3_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM3_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM3_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM3_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM3_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM3_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM3_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM3_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM3_PMSB 3
|
||||
#define SERCOM3_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM3_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM3_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM3_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM3_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM3_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM3_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM3_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM3_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM3_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM3_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM3_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM3_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM3_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM3_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM3_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM3_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM3_USART 1 // USART mode implemented?
|
||||
#define SERCOM3_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM3_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM3_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM3_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM3_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM3_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM4
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM4_INSTANCE_
|
||||
#define _SAMD51_SERCOM4_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM4_INSTANCE_
|
||||
#define _SAME54_SERCOM4_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM4_GCLK_ID_CORE 34
|
||||
#define SERCOM4_GCLK_ID_SLOW 3
|
||||
#define SERCOM4_INT_MSB 6
|
||||
#define SERCOM4_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM4_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM4_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM4_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM4_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM4_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM4_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM4_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM4_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM4_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM4_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM4_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM4_PMSB 3
|
||||
#define SERCOM4_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM4_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM4_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM4_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM4_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM4_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM4_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM4_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM4_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM4_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM4_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM4_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM4_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM4_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM4_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM4_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM4_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM4_USART 1 // USART mode implemented?
|
||||
#define SERCOM4_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM4_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM4_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM4_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM4_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM4_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM5
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM5_INSTANCE_
|
||||
#define _SAMD51_SERCOM5_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM5_INSTANCE_
|
||||
#define _SAME54_SERCOM5_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM5 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM5_GCLK_ID_CORE 35
|
||||
#define SERCOM5_GCLK_ID_SLOW 3
|
||||
#define SERCOM5_INT_MSB 6
|
||||
#define SERCOM5_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM5_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM5_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM5_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM5_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM5_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM5_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM5_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM5_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM5_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM5_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM5_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM5_PMSB 3
|
||||
#define SERCOM5_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM5_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM5_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM5_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM5_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM5_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM5_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM5_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM5_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM5_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM5_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM5_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM5_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM5_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM5_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM5_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM5_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM5_USART 1 // USART mode implemented?
|
||||
#define SERCOM5_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM5_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM5_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM5_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM5_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM5_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM6
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM6_INSTANCE_
|
||||
#define _SAMD51_SERCOM6_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM6_INSTANCE_
|
||||
#define _SAME54_SERCOM6_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM6 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM6_GCLK_ID_CORE 36
|
||||
#define SERCOM6_GCLK_ID_SLOW 3
|
||||
#define SERCOM6_INT_MSB 6
|
||||
#define SERCOM6_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM6_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM6_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM6_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM6_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM6_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM6_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM6_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM6_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM6_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM6_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM6_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM6_PMSB 3
|
||||
#define SERCOM6_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM6_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM6_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM6_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM6_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM6_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM6_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM6_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM6_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM6_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM6_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM6_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM6_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM6_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM6_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM6_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM6_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM6_USART 1 // USART mode implemented?
|
||||
#define SERCOM6_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM6_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM6_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM6_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM6_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM6_INSTANCE_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM7
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
|
@ -27,8 +27,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_SERCOM7_INSTANCE_
|
||||
#define _SAMD51_SERCOM7_INSTANCE_
|
||||
#ifndef _SAME54_SERCOM7_INSTANCE_
|
||||
#define _SAME54_SERCOM7_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM7 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
|
@ -145,6 +145,18 @@
|
|||
#define SERCOM7_GCLK_ID_CORE 37
|
||||
#define SERCOM7_GCLK_ID_SLOW 3
|
||||
#define SERCOM7_INT_MSB 6
|
||||
#define SERCOM7_I2CM 1 // I2C Master mode implemented?
|
||||
#define SERCOM7_I2CS 1 // I2C Slave mode implemented?
|
||||
#define SERCOM7_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
|
||||
#define SERCOM7_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
|
||||
#define SERCOM7_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
|
||||
#define SERCOM7_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
|
||||
#define SERCOM7_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
|
||||
#define SERCOM7_I2C_FASTMP 1 // I2C fast mode plus implemented?
|
||||
#define SERCOM7_I2C_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM7_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
|
||||
#define SERCOM7_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
|
||||
#define SERCOM7_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
|
||||
#define SERCOM7_PMSB 3
|
||||
#define SERCOM7_RETENTION_SUPPORT 0 // Retention supported?
|
||||
#define SERCOM7_SE_CNT 1 // SE counter included?
|
||||
|
|
@ -154,18 +166,6 @@
|
|||
#define SERCOM7_SPI_OZMO 0 // OZMO features implemented?
|
||||
#define SERCOM7_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
|
||||
#define SERCOM7_TTBIT_EXTENSION 1 // 32-bit extension implemented?
|
||||
#define SERCOM7_TWIM 1 // TWI Master mode implemented?
|
||||
#define SERCOM7_TWIS 1 // TWI Slave mode implemented?
|
||||
#define SERCOM7_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
|
||||
#define SERCOM7_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
|
||||
#define SERCOM7_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
|
||||
#define SERCOM7_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
|
||||
#define SERCOM7_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
|
||||
#define SERCOM7_TWI_FASTMP 1 // TWI fast mode plus implemented?
|
||||
#define SERCOM7_TWI_HSMODE 1 // USART mode implemented?
|
||||
#define SERCOM7_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
|
||||
#define SERCOM7_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
|
||||
#define SERCOM7_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
|
||||
#define SERCOM7_USART 1 // USART mode implemented?
|
||||
#define SERCOM7_USART_AUTOBAUD 1 // USART autobaud implemented?
|
||||
#define SERCOM7_USART_COLDET 1 // USART collision detection implemented?
|
||||
|
|
@ -178,4 +178,4 @@
|
|||
#define SERCOM7_USART_SAMPA_EXT 1 // USART sample adjust implemented?
|
||||
#define SERCOM7_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
|
||||
|
||||
#endif /* _SAMD51_SERCOM7_INSTANCE_ */
|
||||
#endif /* _SAME54_SERCOM7_INSTANCE_ */
|
||||
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Reference in New Issue