atsamd: Add support CANbus on ATSAME5x chips
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
0a9becc391
commit
4b77f29c1b
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@ -4,8 +4,8 @@ This document describes Klipper's CAN bus support.
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## Device Hardware
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Klipper currently supports CAN on stm32 and rp2040 chips. In addition,
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the micro-controller chip must be on a board that has a CAN
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Klipper currently supports CAN on stm32, same5x, and rp2040 chips. In
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addition, the micro-controller chip must be on a board that has a CAN
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transceiver.
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To compile for CAN, run `make menuconfig` and select "CAN bus" as the
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@ -68,6 +68,9 @@ config MACH_SAME51
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config MACH_SAME54
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bool
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select MACH_SAMX5
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config HAVE_SAMD_CANBUS
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bool
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default y if MACH_SAME51 || MACH_SAME54
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config MCU
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string
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@ -159,6 +162,48 @@ choice
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config ATSAMD_SERIAL
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bool "Serial"
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select SERIAL
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config ATSAMD_MMENU_CANBUS_PA23_PA22
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bool "CAN bus (on PA23/PA22)"
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depends on HAVE_SAMD_CANBUS
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select CANSERIAL
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config ATSAMD_MMENU_CANBUS_PA25_PA24
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bool "CAN bus (on PA25/PA24)"
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depends on HAVE_SAMD_CANBUS
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select CANSERIAL
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config ATSAMD_MMENU_CANBUS_PB13_PB12
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bool "CAN bus (on PB13/PB12)"
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depends on HAVE_SAMD_CANBUS
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select CANSERIAL
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config ATSAMD_MMENU_CANBUS_PB15_PB14
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bool "CAN bus (on PB15/PB14)"
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depends on HAVE_SAMD_CANBUS
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select CANSERIAL
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config ATSAMD_USBCANBUS
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bool "USB to CAN bus bridge"
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depends on HAVE_SAMD_CANBUS
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select USBCANBUS
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endchoice
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choice
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prompt "CAN bus interface" if USBCANBUS
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config ATSAMD_CMENU_CANBUS_PA23_PA22
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bool "CAN bus (on PA23/PA22)"
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config ATSAMD_CMENU_CANBUS_PB13_PB12
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bool "CAN bus (on PB13/PB12)"
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config ATSAMD_CMENU_CANBUS_PB15_PB14
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bool "CAN bus (on PB15/PB14)"
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endchoice
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config ATSAMD_CANBUS_PA23_PA22
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bool
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default y if ATSAMD_MMENU_CANBUS_PA23_PA22 || ATSAMD_CMENU_CANBUS_PA23_PA22
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config ATSAMD_CANBUS_PA25_PA24
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bool
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default y if ATSAMD_MMENU_CANBUS_PA25_PA24
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config ATSAMD_CANBUS_PB13_PB12
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bool
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default y if ATSAMD_MMENU_CANBUS_PB13_PB12 || ATSAMD_CMENU_CANBUS_PB13_PB12
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config ATSAMD_CANBUS_PB15_PB14
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bool
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default y if ATSAMD_MMENU_CANBUS_PB15_PB14 || ATSAMD_CMENU_CANBUS_PB15_PB14
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endif
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@ -3,7 +3,7 @@
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# Setup the toolchain
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CROSS_PREFIX=arm-none-eabi-
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dirs-y += src/atsamd src/generic
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dirs-y += src/atsamd src/generic lib/fast-hash
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MCU := $(shell echo $(CONFIG_MCU) | tr a-z A-Z)
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@ -11,7 +11,7 @@ CFLAGS-$(CONFIG_MACH_SAMD21) += -mcpu=cortex-m0plus -Ilib/samd21/samd21a/include
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CFLAGS-$(CONFIG_MACH_SAMD51) += -Ilib/samd51/samd51a/include
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CFLAGS-$(CONFIG_MACH_SAME51) += -Ilib/same51/include
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CFLAGS-$(CONFIG_MACH_SAMX5) += -mcpu=cortex-m4 -Ilib/same54/include
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CFLAGS += $(CFLAGS-y) -D__$(MCU)__ -mthumb -Ilib/cmsis-core
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CFLAGS += $(CFLAGS-y) -D__$(MCU)__ -mthumb -Ilib/cmsis-core -Ilib/fast-hash
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CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs
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CFLAGS_klipper.elf += -T $(OUT)src/generic/armcm_link.ld
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@ -22,6 +22,10 @@ src-y += atsamd/main.c atsamd/gpio.c generic/crc16_ccitt.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-$(CONFIG_USBSERIAL) += atsamd/usbserial.c atsamd/chipid.c generic/usb_cdc.c
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src-$(CONFIG_SERIAL) += atsamd/serial.c generic/serial_irq.c
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canbus-src-y := generic/canserial.c ../lib/fast-hash/fasthash.c
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canbus-src-y += atsamd/fdcan.c atsamd/chipid.c
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src-$(CONFIG_USBCANBUS) += $(canbus-src-y) atsamd/usbserial.c generic/usb_canbus.c
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src-$(CONFIG_CANSERIAL) += $(canbus-src-y) generic/canbus.c
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src-$(CONFIG_HAVE_GPIO_ADC) += atsamd/adc.c
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src-$(CONFIG_HAVE_GPIO_I2C) += atsamd/i2c.c
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src-$(CONFIG_HAVE_GPIO_SPI) += atsamd/spi.c
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@ -5,6 +5,7 @@
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_USB_SERIAL_NUMBER_CHIPID
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#include "generic/canserial.h" // canserial_set_uuid
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#include "generic/usb_cdc.h" // usb_fill_serial
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#include "generic/usbstd.h" // usb_string_descriptor
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#include "sched.h" // DECL_INIT
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@ -25,7 +26,7 @@ usbserial_get_serialid(void)
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void
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chipid_init(void)
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{
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if (!CONFIG_USB_SERIAL_NUMBER_CHIPID)
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if (!CONFIG_USB_SERIAL_NUMBER_CHIPID && !CONFIG_CANBUS)
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return;
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uint32_t id[4];
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@ -40,6 +41,11 @@ chipid_init(void)
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id[2] = *(uint32_t*)0x00806014;
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id[3] = *(uint32_t*)0x00806018;
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}
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if (CONFIG_USB_SERIAL_NUMBER_CHIPID)
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usb_fill_serial(&cdc_chipid.desc, ARRAY_SIZE(cdc_chipid.data), id);
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if (CONFIG_CANBUS)
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canserial_set_uuid((void*)id, CHIP_UID_LEN);
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}
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DECL_INIT(chipid_init);
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@ -35,12 +35,14 @@ route_pclock(uint32_t pclk_id, uint32_t clkgen_id)
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// Enable a peripheral clock and power to that peripheral
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void
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enable_pclock(uint32_t pclk_id, uint32_t pm_id)
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enable_pclock(uint32_t pclk_id, int32_t pm_id)
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{
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route_pclock(pclk_id, CLKGEN_MAIN);
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if (pm_id >= 0) {
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uint32_t pm_port = pm_id / 32, pm_bit = 1 << (pm_id % 32);
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(&PM->APBAMASK.reg)[pm_port] |= pm_bit;
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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@ -0,0 +1,293 @@
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// CANbus support on atsame51 chips
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//
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// Copyright (C) 2021-2022 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2019 Eug Krashtan <eug.krashtan@gmail.com>
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// Copyright (C) 2020 Pontus Borg <glpontus@gmail.com>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "command.h" // DECL_CONSTANT_STR
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#include "generic/armcm_boot.h" // armcm_enable_irq
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#include "generic/canbus.h" // canbus_notify_tx
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#include "generic/canserial.h" // CANBUS_ID_ADMIN
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#include "internal.h" // enable_pclock
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#include "sched.h" // DECL_INIT
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/****************************************************************
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* Pin configuration
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****************************************************************/
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#if CONFIG_ATSAMD_CANBUS_PA23_PA22
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PA23,PA22");
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#define GPIO_Rx GPIO('A', 23)
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#define GPIO_Tx GPIO('A', 22)
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#define CANx_GCLK_ID CAN0_GCLK_ID
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#elif CONFIG_ATSAMD_CANBUS_PA25_PA24
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PA25,PA24");
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#define GPIO_Rx GPIO('A', 25)
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#define GPIO_Tx GPIO('A', 24)
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#define CANx_GCLK_ID CAN0_GCLK_ID
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#elif CONFIG_ATSAMD_CANBUS_PB13_PB12
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB13,PB12");
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#define GPIO_Rx GPIO('B', 13)
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#define GPIO_Tx GPIO('B', 12)
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#define CANx_GCLK_ID CAN1_GCLK_ID
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#elif CONFIG_ATSAMD_CANBUS_PB15_PB14
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB15,PB14");
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#define GPIO_Rx GPIO('B', 15)
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#define GPIO_Tx GPIO('B', 14)
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#define CANx_GCLK_ID CAN1_GCLK_ID
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#endif
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#if CANx_GCLK_ID == CAN0_GCLK_ID
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#define CAN_FUNCTION 'I'
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#define CANx CAN0
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#define CANx_IRQn CAN0_IRQn
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#else
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#define CAN_FUNCTION 'H'
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#define CANx CAN1
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#define CANx_IRQn CAN1_IRQn
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#endif
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/****************************************************************
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* Message ram layout
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****************************************************************/
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struct fdcan_fifo {
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uint32_t id_section;
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uint32_t dlc_section;
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uint32_t data[64 / 4];
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};
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#define FDCAN_XTD (1<<30)
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#define FDCAN_RTR (1<<29)
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struct fdcan_msg_ram {
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uint32_t FLS[28]; // Filter list standard
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uint32_t FLE[16]; // Filter list extended
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struct fdcan_fifo RXF0[3];
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struct fdcan_fifo RXF1[3];
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uint32_t TEF[6]; // Tx event FIFO
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struct fdcan_fifo TXFIFO[3];
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};
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// Message ram is in regular memory
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static struct fdcan_msg_ram MSG_RAM;
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/****************************************************************
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* CANbus code
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****************************************************************/
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#define FDCAN_IE_TC (CAN_IE_TCE | CAN_IE_TCFE | CAN_IE_TFEE)
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// Transmit a packet
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int
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canbus_send(struct canbus_msg *msg)
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{
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uint32_t txfqs = CANx->TXFQS.reg;
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if (txfqs & CAN_TXFQS_TFQF)
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// No space in transmit fifo - wait for irq
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return -1;
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uint32_t w_index = ((txfqs & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos);
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struct fdcan_fifo *txfifo = &MSG_RAM.TXFIFO[w_index];
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uint32_t ids;
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if (msg->id & CANMSG_ID_EFF)
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ids = (msg->id & 0x1fffffff) | FDCAN_XTD;
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else
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ids = (msg->id & 0x7ff) << 18;
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ids |= msg->id & CANMSG_ID_RTR ? FDCAN_RTR : 0;
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txfifo->id_section = ids;
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txfifo->dlc_section = (msg->dlc & 0x0f) << 16;
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txfifo->data[0] = msg->data32[0];
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txfifo->data[1] = msg->data32[1];
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barrier();
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CANx->TXBAR.reg = ((uint32_t)1 << w_index);
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return CANMSG_DATA_LEN(msg);
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}
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static void
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can_filter(uint32_t index, uint32_t id)
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{
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MSG_RAM.FLS[index] = ((0x2 << 30) // Classic filter
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| (0x1 << 27) // Store in Rx FIFO 0 if filter matches
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| (id << 16)
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| 0x7FF); // mask all enabled
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}
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// Setup the receive packet filter
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void
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canbus_set_filter(uint32_t id)
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{
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if (!CONFIG_CANBUS_FILTER)
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return;
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/* Request initialisation */
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CANx->CCCR.reg |= CAN_CCCR_INIT;
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/* Wait the acknowledge */
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while (!(CANx->CCCR.reg & CAN_CCCR_INIT))
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;
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/* Enable configuration change */
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CANx->CCCR.reg |= CAN_CCCR_CCE;
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// Load filter
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can_filter(0, CANBUS_ID_ADMIN);
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can_filter(1, id);
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can_filter(2, id + 1);
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uint32_t flssa = (uint32_t)MSG_RAM.FLS - CAN0_MSG_RAM_ADDR;
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CANx->SIDFC.reg = flssa | ((id ? 3 : 1) << CAN_SIDFC_LSS_Pos);
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CANx->GFC.reg = 0x02 << CAN_GFC_ANFS_Pos;
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/* Leave the initialisation mode for the filter */
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barrier();
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CANx->CCCR.reg &= ~CAN_CCCR_CCE;
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CANx->CCCR.reg &= ~CAN_CCCR_INIT;
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}
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// This function handles CAN global interrupts
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void
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CAN_IRQHandler(void)
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{
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uint32_t ir = CANx->IR.reg;
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if (ir & CAN_IE_RF0NE) {
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CANx->IR.reg = CAN_IE_RF0NE;
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uint32_t rxf0s = CANx->RXF0S.reg;
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if (rxf0s & CAN_RXF0S_F0FL_Msk) {
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// Read and ack data packet
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uint32_t idx = (rxf0s & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos;
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struct fdcan_fifo *rxf0 = &MSG_RAM.RXF0[idx];
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uint32_t ids = rxf0->id_section;
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struct canbus_msg msg;
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if (ids & FDCAN_XTD)
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msg.id = (ids & 0x1fffffff) | CANMSG_ID_EFF;
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else
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msg.id = (ids >> 18) & 0x7ff;
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msg.id |= ids & FDCAN_RTR ? CANMSG_ID_RTR : 0;
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msg.dlc = (rxf0->dlc_section >> 16) & 0x0f;
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msg.data32[0] = rxf0->data[0];
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msg.data32[1] = rxf0->data[1];
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barrier();
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CANx->RXF0A.reg = idx;
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// Process packet
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canbus_process_data(&msg);
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}
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}
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if (ir & FDCAN_IE_TC) {
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// Tx
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CANx->IR.reg = FDCAN_IE_TC;
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canbus_notify_tx();
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}
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}
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static inline const uint32_t
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make_btr(uint32_t sjw, // Sync jump width, ... hmm
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uint32_t time_seg1, // time segment before sample point, 1 .. 16
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uint32_t time_seg2, // time segment after sample point, 1 .. 8
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uint32_t brp) // Baud rate prescaler, 1 .. 1024
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{
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return (((uint32_t)(sjw-1)) << CAN_NBTP_NSJW_Pos
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| ((uint32_t)(time_seg1-1)) << CAN_NBTP_NTSEG1_Pos
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| ((uint32_t)(time_seg2-1)) << CAN_NBTP_NTSEG2_Pos
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| ((uint32_t)(brp - 1)) << CAN_NBTP_NBRP_Pos);
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}
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static inline const uint32_t
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compute_btr(uint32_t pclock, uint32_t bitrate)
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{
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/*
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Some equations:
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Tpclock = 1 / pclock
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Tq = brp * Tpclock
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Tbs1 = Tq * TS1
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Tbs2 = Tq * TS2
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NominalBitTime = Tq + Tbs1 + Tbs2
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BaudRate = 1/NominalBitTime
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Bit value sample point is after Tq+Tbs1. Ideal sample point
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is at 87.5% of NominalBitTime
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Use the lowest brp where ts1 and ts2 are in valid range
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*/
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uint32_t bit_clocks = pclock / bitrate; // clock ticks per bit
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uint32_t sjw = 2;
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uint32_t qs;
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// Find number of time quantas that gives us the exact wanted bit time
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for (qs = 18; qs > 9; qs--) {
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// check that bit_clocks / quantas is an integer
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uint32_t brp_rem = bit_clocks % qs;
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if (brp_rem == 0)
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break;
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}
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uint32_t brp = bit_clocks / qs;
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uint32_t time_seg2 = qs / 8; // sample at ~87.5%
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uint32_t time_seg1 = qs - (1 + time_seg2);
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return make_btr(sjw, time_seg1, time_seg2, brp);
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}
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void
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can_init(void)
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{
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if (!CONFIG_USB) {
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// The FDCAN peripheral only seems to run if at least one
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// other peripheral is also enabled.
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enable_pclock(USB_GCLK_ID, ID_USB);
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USB->DEVICE.CTRLA.reg = USB_CTRLA_ENABLE;
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}
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enable_pclock(CANx_GCLK_ID, -1);
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gpio_peripheral(GPIO_Rx, CAN_FUNCTION, 1);
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gpio_peripheral(GPIO_Tx, CAN_FUNCTION, 0);
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uint32_t pclock = get_pclock_frequency(CANx_GCLK_ID);
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uint32_t btr = compute_btr(pclock, CONFIG_CANBUS_FREQUENCY);
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/*##-1- Configure the CAN #######################################*/
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/* Exit from sleep mode */
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CANx->CCCR.reg &= ~CAN_CCCR_CSR;
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/* Wait the acknowledge */
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while (CANx->CCCR.reg & CAN_CCCR_CSA)
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;
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/* Request initialisation */
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CANx->CCCR.reg |= CAN_CCCR_INIT;
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/* Wait the acknowledge */
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while (!(CANx->CCCR.reg & CAN_CCCR_INIT))
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||||
;
|
||||
/* Enable configuration change */
|
||||
CANx->CCCR.reg |= CAN_CCCR_CCE;
|
||||
|
||||
/* Disable protocol exception handling */
|
||||
CANx->CCCR.reg |= CAN_CCCR_PXHD;
|
||||
|
||||
CANx->NBTP.reg = btr;
|
||||
|
||||
/* Setup message RAM addresses */
|
||||
uint32_t f0sa = (uint32_t)MSG_RAM.RXF0 - CAN0_MSG_RAM_ADDR;
|
||||
CANx->RXF0C.reg = f0sa | (ARRAY_SIZE(MSG_RAM.RXF0) << CAN_RXF0C_F0S_Pos);
|
||||
CANx->RXESC.reg = (7 << CAN_RXESC_F1DS_Pos) | (7 << CAN_RXESC_F0DS_Pos);
|
||||
uint32_t tbsa = (uint32_t)MSG_RAM.TXFIFO - CAN0_MSG_RAM_ADDR;
|
||||
CANx->TXBC.reg = tbsa | (ARRAY_SIZE(MSG_RAM.TXFIFO) << CAN_TXBC_TFQS_Pos);
|
||||
CANx->TXESC.reg = 7 << CAN_TXESC_TBDS_Pos;
|
||||
|
||||
/* Leave the initialisation mode */
|
||||
CANx->CCCR.reg &= ~CAN_CCCR_CCE;
|
||||
CANx->CCCR.reg &= ~CAN_CCCR_INIT;
|
||||
|
||||
/*##-2- Configure the CAN Filter #######################################*/
|
||||
canbus_set_filter(0);
|
||||
|
||||
/*##-3- Configure Interrupts #################################*/
|
||||
armcm_enable_irq(CAN_IRQHandler, CANx_IRQn, 1);
|
||||
CANx->ILE.reg = CAN_ILE_EINT0;
|
||||
CANx->IE.reg = CAN_IE_RF0NE | FDCAN_IE_TC;
|
||||
}
|
||||
DECL_INIT(can_init);
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
#define GET_FUSE(REG) \
|
||||
((*((uint32_t*)(REG##_ADDR)) & (REG##_Msk)) >> (REG##_Pos))
|
||||
|
||||
void enable_pclock(uint32_t pclk_id, uint32_t pm_id);
|
||||
void enable_pclock(uint32_t pclk_id, int32_t pm_id);
|
||||
uint32_t get_pclock_frequency(uint32_t pclk_id);
|
||||
void gpio_peripheral(uint32_t gpio, char ptype, int32_t pull_up);
|
||||
|
||||
|
|
|
|||
|
|
@ -39,12 +39,14 @@ route_pclock(uint32_t pclk_id, uint32_t clkgen_id)
|
|||
|
||||
// Enable a peripheral clock and power to that peripheral
|
||||
void
|
||||
enable_pclock(uint32_t pclk_id, uint32_t pm_id)
|
||||
enable_pclock(uint32_t pclk_id, int32_t pm_id)
|
||||
{
|
||||
route_pclock(pclk_id, CLKGEN_48M);
|
||||
if (pm_id >= 0) {
|
||||
uint32_t pm_port = pm_id / 32, pm_bit = 1 << (pm_id % 32);
|
||||
(&MCLK->APBAMASK.reg)[pm_port] |= pm_bit;
|
||||
}
|
||||
}
|
||||
|
||||
// Return the frequency of the given peripheral clock
|
||||
uint32_t
|
||||
|
|
|
|||
Loading…
Reference in New Issue