stm32: Support for USART5 on STM32G0B1 (#6105)
Support for USART5 on PD2,3 Add exception on RCC bits for USART5&6 Signed-off-by: Florin Popescu <florinsgpopescu@gmail.com>
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@ -400,6 +400,10 @@ choice
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bool "Serial (on UART4 PA0/PA1)"
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depends on MACH_STM32H7
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select SERIAL
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config STM32_SERIAL_USART5
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bool "Serial (on USART5 PD2/PD3)" if LOW_LEVEL_OPTIONS
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depends on MACH_STM32G0Bx
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select SERIAL
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config STM32_CANBUS_PA11_PA12
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bool "CAN bus (on PA11/PA12)"
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depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS
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@ -78,6 +78,13 @@
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#define USARTx_FUNCTION GPIO_FUNCTION(8)
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#define USARTx UART4
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#define USARTx_IRQn UART4_IRQn
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#elif CONFIG_STM32_SERIAL_USART5
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD2,PD3");
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#define GPIO_Rx GPIO('D', 2)
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#define GPIO_Tx GPIO('D', 3)
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#define USARTx_FUNCTION GPIO_FUNCTION(3)
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#define USARTx USART5
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#define USARTx_IRQn USART5_IRQn
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#endif
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#if CONFIG_MACH_STM32F031
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@ -90,6 +97,10 @@
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// Some of the stm32g0 MCUs have slightly different register names
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#if CONFIG_MACH_STM32G0B1
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#define USART2_IRQn USART2_LPUART2_IRQn
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#define USART3_IRQn USART3_4_5_6_LPUART1_IRQn
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#define USART4_IRQn USART3_4_5_6_LPUART1_IRQn
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#define USART5_IRQn USART3_4_5_6_LPUART1_IRQn
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#define USART6_IRQn USART3_4_5_6_LPUART1_IRQn
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#endif
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#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
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#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
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@ -32,6 +32,14 @@ lookup_clock_line(uint32_t periph_base)
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uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHBENR, .rst=&RCC->AHBRSTR, .bit=bit};
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}
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#ifdef USART5_BASE
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if (periph_base == USART5_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<8};
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#endif
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#ifdef USART6_BASE
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if (periph_base == USART6_BASE)
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<9};
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#endif
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#if defined(FDCAN1_BASE) || defined(FDCAN2_BASE)
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if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE))
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return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12};
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