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stm32: Support for USART5 on STM32G0B1 (#6105) 

Support for USART5 on PD2,3

Add exception on RCC bits for USART5&6

Signed-off-by: Florin Popescu <florinsgpopescu@gmail.com>
This commit is contained in:
Florin Popescu 2023-04-19 17:47:18 +02:00 committed by GitHub
parent cba119db3a
commit 40b4b34998
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 23 additions and 0 deletions
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4
src/stm32/Kconfig
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@ -400,6 +400,10 @@ choice
bool "Serial (on UART4 PA0/PA1)" bool "Serial (on UART4 PA0/PA1)"
depends on MACH_STM32H7 depends on MACH_STM32H7
select SERIAL select SERIAL
config STM32_SERIAL_USART5
bool "Serial (on USART5 PD2/PD3)" if LOW_LEVEL_OPTIONS
depends on MACH_STM32G0Bx
select SERIAL
config STM32_CANBUS_PA11_PA12 config STM32_CANBUS_PA11_PA12
bool "CAN bus (on PA11/PA12)" bool "CAN bus (on PA11/PA12)"
depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS

11
src/stm32/stm32f0_serial.c
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@ -78,6 +78,13 @@
#define USARTx_FUNCTION GPIO_FUNCTION(8) #define USARTx_FUNCTION GPIO_FUNCTION(8)
#define USARTx UART4 #define USARTx UART4
#define USARTx_IRQn UART4_IRQn #define USARTx_IRQn UART4_IRQn
#elif CONFIG_STM32_SERIAL_USART5
DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD2,PD3");
#define GPIO_Rx GPIO('D', 2)
#define GPIO_Tx GPIO('D', 3)
#define USARTx_FUNCTION GPIO_FUNCTION(3)
#define USARTx USART5
#define USARTx_IRQn USART5_IRQn
#endif #endif
#if CONFIG_MACH_STM32F031 #if CONFIG_MACH_STM32F031
@ -90,6 +97,10 @@
// Some of the stm32g0 MCUs have slightly different register names // Some of the stm32g0 MCUs have slightly different register names
#if CONFIG_MACH_STM32G0B1 #if CONFIG_MACH_STM32G0B1
#define USART2_IRQn USART2_LPUART2_IRQn #define USART2_IRQn USART2_LPUART2_IRQn
#define USART3_IRQn USART3_4_5_6_LPUART1_IRQn
#define USART4_IRQn USART3_4_5_6_LPUART1_IRQn
#define USART5_IRQn USART3_4_5_6_LPUART1_IRQn
#define USART6_IRQn USART3_4_5_6_LPUART1_IRQn
#endif #endif
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE

8
src/stm32/stm32g0.c
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@ -32,6 +32,14 @@ lookup_clock_line(uint32_t periph_base)
uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400); uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400);
return (struct cline){.en=&RCC->AHBENR, .rst=&RCC->AHBRSTR, .bit=bit}; return (struct cline){.en=&RCC->AHBENR, .rst=&RCC->AHBRSTR, .bit=bit};
} }
#ifdef USART5_BASE
if (periph_base == USART5_BASE)
return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<8};
#endif
#ifdef USART6_BASE
if (periph_base == USART6_BASE)
return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<9};
#endif
#if defined(FDCAN1_BASE) || defined(FDCAN2_BASE) #if defined(FDCAN1_BASE) || defined(FDCAN2_BASE)
if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE)) if ((periph_base == FDCAN1_BASE) || (periph_base == FDCAN2_BASE))
return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12}; return (struct cline){.en=&RCC->APBENR1,.rst=&RCC->APBRSTR1,.bit=1<<12};