atsam: Add support for "timer" controlled hardware pwm pins
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
f96239019a
commit
3910a44cc9
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@ -25,7 +25,7 @@ struct gpio_pwm {
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void *reg;
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};
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struct gpio_pwm gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val);
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void gpio_pwm_write(struct gpio_pwm g, uint8_t val);
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void gpio_pwm_write(struct gpio_pwm g, uint32_t val);
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struct gpio_adc {
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uint32_t chan;
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@ -4,11 +4,149 @@
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/irq.h" // irq_save
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#include "command.h" // shutdown
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#include "gpio.h" // gpio_pwm_write
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#include "internal.h" // GPIO
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#include "sched.h" // sched_shutdown
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#define MAX_PWM 255
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DECL_CONSTANT("PWM_MAX", MAX_PWM);
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/****************************************************************
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* TC hardware device
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****************************************************************/
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struct gpio_tc_info {
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uint8_t gpio, ptype, id;
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volatile void *reg;
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};
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static const struct gpio_tc_info tc_regs[] = {
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#if CONFIG_MACH_SAM3X
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{ GPIO('B', 25), 'B', ID_TC0, &TC0->TC_CHANNEL[0].TC_RA },
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{ GPIO('A', 2), 'A', ID_TC1, &TC0->TC_CHANNEL[1].TC_RA },
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{ GPIO('A', 5), 'A', ID_TC2, &TC0->TC_CHANNEL[2].TC_RA },
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{ GPIO('B', 27), 'B', ID_TC0, &TC0->TC_CHANNEL[0].TC_RB },
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{ GPIO('A', 3), 'A', ID_TC1, &TC0->TC_CHANNEL[1].TC_RB },
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{ GPIO('A', 6), 'A', ID_TC2, &TC0->TC_CHANNEL[2].TC_RB },
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{ GPIO('B', 0), 'B', ID_TC3, &TC1->TC_CHANNEL[0].TC_RA },
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{ GPIO('B', 2), 'B', ID_TC4, &TC1->TC_CHANNEL[1].TC_RA },
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{ GPIO('B', 4), 'B', ID_TC5, &TC1->TC_CHANNEL[2].TC_RA },
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{ GPIO('B', 1), 'B', ID_TC3, &TC1->TC_CHANNEL[0].TC_RB },
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{ GPIO('B', 3), 'B', ID_TC4, &TC1->TC_CHANNEL[1].TC_RB },
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{ GPIO('B', 5), 'B', ID_TC5, &TC1->TC_CHANNEL[2].TC_RB },
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#if CONFIG_MACH_SAM3X8E
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{ GPIO('C', 25), 'B', ID_TC6, &TC2->TC_CHANNEL[0].TC_RA },
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{ GPIO('C', 28), 'B', ID_TC7, &TC2->TC_CHANNEL[1].TC_RA },
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{ GPIO('D', 7), 'B', ID_TC8, &TC2->TC_CHANNEL[2].TC_RA },
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{ GPIO('C', 26), 'B', ID_TC6, &TC2->TC_CHANNEL[0].TC_RB },
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{ GPIO('C', 29), 'B', ID_TC7, &TC2->TC_CHANNEL[1].TC_RB },
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{ GPIO('D', 8), 'B', ID_TC8, &TC2->TC_CHANNEL[2].TC_RB },
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#endif
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#elif CONFIG_MACH_SAM4
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{ GPIO('A', 0), 'B', ID_TC0, &TC0->TC_CHANNEL[0].TC_RA },
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{ GPIO('A', 15), 'B', ID_TC1, &TC0->TC_CHANNEL[1].TC_RA },
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{ GPIO('A', 26), 'B', ID_TC2, &TC0->TC_CHANNEL[2].TC_RA },
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{ GPIO('A', 1), 'B', ID_TC0, &TC0->TC_CHANNEL[0].TC_RB },
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{ GPIO('A', 16), 'B', ID_TC1, &TC0->TC_CHANNEL[1].TC_RB },
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{ GPIO('A', 27), 'B', ID_TC2, &TC0->TC_CHANNEL[2].TC_RB },
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{ GPIO('C', 23), 'B', ID_TC3, &TC1->TC_CHANNEL[0].TC_RA },
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{ GPIO('C', 26), 'B', ID_TC4, &TC1->TC_CHANNEL[1].TC_RA },
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{ GPIO('C', 29), 'B', ID_TC5, &TC1->TC_CHANNEL[2].TC_RA },
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{ GPIO('C', 24), 'B', ID_TC3, &TC1->TC_CHANNEL[0].TC_RB },
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{ GPIO('C', 27), 'B', ID_TC4, &TC1->TC_CHANNEL[1].TC_RB },
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{ GPIO('C', 30), 'B', ID_TC5, &TC1->TC_CHANNEL[2].TC_RB },
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#if CONFIG_MACH_SAM4E8E
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{ GPIO('C', 5), 'B', ID_TC6, &TC2->TC_CHANNEL[0].TC_RA },
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{ GPIO('C', 8), 'B', ID_TC7, &TC2->TC_CHANNEL[1].TC_RA },
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{ GPIO('C', 11), 'B', ID_TC8, &TC2->TC_CHANNEL[2].TC_RA },
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{ GPIO('C', 6), 'B', ID_TC6, &TC2->TC_CHANNEL[0].TC_RB },
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{ GPIO('C', 9), 'B', ID_TC7, &TC2->TC_CHANNEL[1].TC_RB },
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{ GPIO('C', 12), 'B', ID_TC8, &TC2->TC_CHANNEL[2].TC_RB },
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#endif
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#endif
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};
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static inline int tc_is_tc(struct gpio_pwm g) {
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return (((uint32_t)g.reg & ~0xffff) == ((uint32_t)TC0 & ~0xffff));
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}
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static inline TcChannel *tc_from_reg(struct gpio_pwm g) {
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return (void*)((uint32_t)g.reg & ~0x3f);
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}
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static inline int tc_is_b(struct gpio_pwm g) {
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return (((uint32_t)g.reg & 0x3f)
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== ((uint32_t)&TC0->TC_CHANNEL[0].TC_RB & 0x3f));
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}
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static void
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gpio_tc_write(struct gpio_pwm g, uint32_t val)
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{
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TcChannel *tc = tc_from_reg(g);
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uint32_t mask = TC_CMR_ACPA_Msk | TC_CMR_ACPC_Msk;
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uint32_t bits = TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET;
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if (!val)
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bits = TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_CLEAR;
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else if (val >= MAX_PWM)
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bits = TC_CMR_ACPA_SET | TC_CMR_ACPC_SET;
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if (tc_is_b(g)) {
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mask <<= 8;
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bits <<= 8;
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}
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irqstatus_t flag = irq_save();
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tc->TC_CMR = (tc->TC_CMR & ~mask) | bits;
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*(volatile uint32_t*)g.reg = val;
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irq_restore(flag);
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}
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static struct gpio_pwm
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gpio_tc_setup(uint8_t pin, uint32_t cycle_time, uint8_t val)
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{
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// Find pin in tc_regs table
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const struct gpio_tc_info *p = tc_regs;
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for (; ; p++) {
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if (p >= &tc_regs[ARRAY_SIZE(tc_regs)])
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shutdown("Not a valid PWM pin");
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if (p->gpio == pin)
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break;
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}
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// Map cycle_time to clock divisor
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uint32_t div = TC_CMR_TCCLKS_TIMER_CLOCK4;
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if (cycle_time < (MAX_PWM*8 + MAX_PWM*2) / 2)
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div = TC_CMR_TCCLKS_TIMER_CLOCK1;
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else if (cycle_time < (MAX_PWM*32 + MAX_PWM*8) / 2)
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div = TC_CMR_TCCLKS_TIMER_CLOCK2;
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else if (cycle_time < (MAX_PWM*128 + MAX_PWM*32) / 2)
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div = TC_CMR_TCCLKS_TIMER_CLOCK3;
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// Enable clock
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enable_pclock(p->id);
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// Enable PWM output
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struct gpio_pwm g = (struct gpio_pwm){ (void*)p->reg };
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TcChannel *tc = tc_from_reg(g);
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uint32_t prev_cmr = tc->TC_CMR;
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if (prev_cmr && (prev_cmr & TC_CMR_TCCLKS_Msk) != div)
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shutdown("PWM already programmed at different speed");
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gpio_peripheral(pin, p->ptype, 0);
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if (prev_cmr) {
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gpio_tc_write(g, val);
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} else {
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tc->TC_CMR = TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | div | TC_CMR_EEVT_XC0;
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gpio_tc_write(g, val);
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tc->TC_RC = MAX_PWM;
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tc->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
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}
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return g;
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}
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/****************************************************************
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* PWM hardware device
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****************************************************************/
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struct gpio_pwm_info {
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uint8_t gpio, channel, ptype;
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};
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@ -52,10 +190,6 @@ static const struct gpio_pwm_info pwm_regs[] = {
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#endif
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};
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#define MAX_PWM 255
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DECL_CONSTANT("PWM_MAX", MAX_PWM);
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struct gpio_pwm
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gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val)
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{
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@ -63,7 +197,7 @@ gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val)
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const struct gpio_pwm_info *p = pwm_regs;
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for (; ; p++) {
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if (p >= &pwm_regs[ARRAY_SIZE(pwm_regs)])
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shutdown("Not a valid PWM pin");
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return gpio_tc_setup(pin, cycle_time, val);
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if (p->gpio == pin)
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break;
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}
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@ -90,7 +224,10 @@ gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val)
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}
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void
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gpio_pwm_write(struct gpio_pwm g, uint8_t val)
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gpio_pwm_write(struct gpio_pwm g, uint32_t val)
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{
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*(volatile uint32_t*)g.reg = val;
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if (tc_is_tc(g))
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gpio_tc_write(g, val);
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else
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*(volatile uint32_t*)g.reg = val;
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}
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