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stm32: add PB5/PB6 as CAN pins - required for BTT U2C v2.x 

Signed-off-by: Stefan Dej <meteyou@gmail.com>
This commit is contained in:
Stefan Dej 2023-05-17 21:42:50 +02:00 committed by KevinOConnor
parent 7511151ac9
commit 37315bf336
2 changed files with 6 additions and 2 deletions
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2
src/stm32/Kconfig
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@ -473,7 +473,7 @@ choice
depends on HAVE_STM32_CANBUS && MACH_STM32F4 depends on HAVE_STM32_CANBUS && MACH_STM32F4
config STM32_CMENU_CANBUS_PB5_PB6 config STM32_CMENU_CANBUS_PB5_PB6
bool "CAN bus (on PB5/PB6)" bool "CAN bus (on PB5/PB6)"
depends on HAVE_STM32_CANBUS && MACH_STM32F4 depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || (HAVE_STM32_FDCANBUS && MACH_STM32G0B1)
config STM32_CMENU_CANBUS_PB12_PB13 config STM32_CMENU_CANBUS_PB12_PB13
bool "CAN bus (on PB12/PB13)" bool "CAN bus (on PB12/PB13)"
depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || HAVE_STM32_FDCANBUS depends on (HAVE_STM32_CANBUS && MACH_STM32F4) || HAVE_STM32_FDCANBUS

6
src/stm32/fdcan.c
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@ -46,6 +46,10 @@
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3"); DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3");
#define GPIO_Rx GPIO('C', 2) #define GPIO_Rx GPIO('C', 2)
#define GPIO_Tx GPIO('C', 3) #define GPIO_Tx GPIO('C', 3)
#elif CONFIG_STM32_CANBUS_PB5_PB6
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB5,PB6");
#define GPIO_Rx GPIO('B', 5)
#define GPIO_Tx GPIO('B', 6)
#elif CONFIG_STM32_CANBUS_PB12_PB13 #elif CONFIG_STM32_CANBUS_PB12_PB13
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13"); DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
#define GPIO_Rx GPIO('B', 12) #define GPIO_Rx GPIO('B', 12)
@ -53,7 +57,7 @@
#endif #endif
#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3 \ #if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3 \
|| CONFIG_STM32_CANBUS_PB12_PB13) || CONFIG_STM32_CANBUS_PB5_PB6 ||CONFIG_STM32_CANBUS_PB12_PB13)
#define SOC_CAN FDCAN1 #define SOC_CAN FDCAN1
#define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1) #define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1)
#else #else