stm32f7: add support for stm32f7 and remram board
Signed-off-by: Frederic Morin <frederic.morin.8@gmail.com>
This commit is contained in:
Frederic Morin
KevinOConnor
parent
a3eebab4f2
commit
33b18fd62b
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# This file contains common pin mappings for remram boards. To use this
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# config, the firmware should be compiled for the ST stm32f765.
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# See docs/Config_Reference.md for a description of parameters.
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[mcu]
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serial: /dev/ttyACM0
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[printer]
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kinematics: cartesian
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max_velocity: 300
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max_accel: 3000
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max_z_velocity: 5
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max_z_accel: 100
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[stepper_x]
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step_pin: PA15
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dir_pin: PC10
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enable_pin: !PC12
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microsteps: 16
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rotation_distance: 40
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endstop_pin: ^!PB12 # X_MIN
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position_endstop: 0
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position_max: 200
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homing_speed: 10
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[tmc2130 stepper_x]
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cs_pin: PB1
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spi_bus: spi1
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run_current: 0.600
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stealthchop_threshold: 999999
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diag1_pin: ^!PC11
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[stepper_y]
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step_pin: PB3
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dir_pin: !PD6
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enable_pin: !PD4
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microsteps: 16
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rotation_distance: 40
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endstop_pin: ^!PB14 # Y_MIN
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position_endstop: 0
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position_max: 200
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homing_speed: 10
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[tmc2130 stepper_y]
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cs_pin: PB0
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spi_bus: spi1
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run_current: 0.600
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stealthchop_threshold: 999999
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diag1_pin: ^!PD5
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[stepper_z]
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step_pin: PB10
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dir_pin: PE13
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enable_pin: !PE15
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microsteps: 16
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rotation_distance: 8
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endstop_pin: ^!PD8 # Z_MIN
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position_endstop: 0.5
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position_max: 200
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homing_speed: 10
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[tmc2130 stepper_z]
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cs_pin: PC5
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spi_bus: spi1
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run_current: 0.600
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stealthchop_threshold: 999999
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diag1_pin: ^!PE14
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[extruder]
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step_pin: PB11
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dir_pin: PE10
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enable_pin: !PE11
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microsteps: 16
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rotation_distance: 33.500
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nozzle_diameter: 0.400
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filament_diameter: 1.750
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heater_pin: PA3 # HEATER
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sensor_type: Generic 3950
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sensor_pin: PC1 # TEMP2
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control: pid
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pid_Kp: 22.2
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pid_Ki: 1.08
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pid_Kd: 114
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min_temp: 0
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max_temp: 250
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[tmc2130 extruder]
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cs_pin: PC4
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spi_bus: spi1
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run_current: 0.600
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stealthchop_threshold: 999999
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diag1_pin: ^!PE12
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[heater_fan hotend_fan]
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pin: PA2 # FAN2
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[heater_bed]
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heater_pin: PA1 # BED OUT
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sensor_type: Generic 3950
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sensor_pin: PC0 # TEMP1
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control: watermark
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min_temp: 0
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max_temp: 130
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[fan] # Print cooling fan.
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pin: PA0 # FAN1
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# [temperature_sensor temp3]
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# sensor_type: Generic 3950
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# sensor_pin: PC2 # TEMP3
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# min_temp: 0
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# max_temp: 300
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# gcode_id: temp3
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[static_digital_output yellow_led]
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pins: !PD0 # STATUS LED
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@ -78,6 +78,11 @@ The stm32f4 directory contains code from:
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version v1.24.1 (b5abca20c9676b04f8d2885a668a9b653ee65705). Contents
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taken from the Drivers/CMSIS/Device/ST/STM32F4xx/ directory.
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The stm32f7 directory contains code from:
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https://github.com/STMicroelectronics/STM32CubeF7
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version v1.15.0 (3600603267ebc7da619f50542e99bbdfd7e35f4a). Contents
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taken from the Drivers/CMSIS/Device/ST/STM32F7xx/ directory.
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The stm32g0 directory contains code from:
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https://github.com/STMicroelectronics/STM32CubeG0
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version v1.4.1 (5cb06333a6a43cefbe145f10a5aa98d3cc4cffee). Contents
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/**
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******************************************************************************
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* @file stm32f7xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32F7xx device used in the target application
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* - To use or not the peripheral’s drivers in application code(i.e.
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* code will be based on direct access to peripheral’s registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f7xx
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* @{
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*/
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#ifndef __STM32F7xx_H
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#define __STM32F7xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32F7)
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#define STM32F7
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#endif /* STM32F7 */
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/* Uncomment the line below according to the target STM32 device used in your
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application
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*/
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#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
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!defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
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!defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && !defined (STM32F730xx) && \
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!defined (STM32F750xx)
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/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
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STM32F756NG Devices */
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/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
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STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
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/* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
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/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
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STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
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/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
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STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
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/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
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STM32F769NG, STM32F769NI, STM32F768AI Devices */
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/* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
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/* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
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/* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
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STM32F722VC, STM32F722RC Devices */
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/* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
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/* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
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/* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
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/* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */
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/* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V1.2.4
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*/
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#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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#define __STM32F7_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
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#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
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|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
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|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
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|(__STM32F7_CMSIS_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32F722xx)
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#include "stm32f722xx.h"
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#elif defined(STM32F723xx)
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#include "stm32f723xx.h"
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#elif defined(STM32F732xx)
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#include "stm32f732xx.h"
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#elif defined(STM32F733xx)
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#include "stm32f733xx.h"
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#elif defined(STM32F756xx)
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#include "stm32f756xx.h"
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#elif defined(STM32F746xx)
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#include "stm32f746xx.h"
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#elif defined(STM32F745xx)
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#include "stm32f745xx.h"
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#elif defined(STM32F765xx)
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#include "stm32f765xx.h"
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#elif defined(STM32F767xx)
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#include "stm32f767xx.h"
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#elif defined(STM32F769xx)
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#include "stm32f769xx.h"
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#elif defined(STM32F777xx)
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#include "stm32f777xx.h"
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#elif defined(STM32F779xx)
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#include "stm32f779xx.h"
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#elif defined(STM32F730xx)
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#include "stm32f730xx.h"
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#elif defined(STM32F750xx)
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#include "stm32f750xx.h"
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#else
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#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0U,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0U,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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SUCCESS = 0U,
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ERROR = !SUCCESS
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macro
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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/**
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* @}
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*/
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#ifdef USE_HAL_DRIVER
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#include "stm32f7xx_hal.h"
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#endif /* USE_HAL_DRIVER */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __STM32F7xx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -0,0 +1,123 @@
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/**
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******************************************************************************
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* @file system_stm32f7xx.h
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* @author MCD Application Team
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* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
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*
|
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* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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******************************************************************************
|
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f7xx_system
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* @{
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*/
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/**
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* @brief Define to prevent recursive inclusion
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*/
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#ifndef __SYSTEM_STM32F7XX_H
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#define __SYSTEM_STM32F7XX_H
|
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#ifdef __cplusplus
|
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extern "C" {
|
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#endif
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|
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/** @addtogroup STM32F7xx_System_Includes
|
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* @{
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*/
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/**
|
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* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Variables
|
||||
* @{
|
||||
*/
|
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F7XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f7xx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f7xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f7xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 16000000;
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -345,6 +345,7 @@ MCUTYPES = {
|
|||
'lpc176': flash_lpc176x, 'stm32f103': flash_stm32f1,
|
||||
'stm32f4': flash_stm32f4, 'stm32f042': flash_stm32f4,
|
||||
'stm32f072': flash_stm32f4, 'stm32g0b1': flash_stm32f4,
|
||||
'stm32f7': flash_stm32f4,
|
||||
'stm32h7': flash_stm32f4, 'stm32l4': flash_stm32f4,
|
||||
'stm32g4': flash_stm32f4, 'rp2040': flash_rp2040,
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ config STM32_SELECT
|
|||
select HAVE_GPIO_I2C if !(MACH_STM32F031)
|
||||
select HAVE_GPIO_SPI if !MACH_STM32F031
|
||||
select HAVE_GPIO_SDIO if MACH_STM32F4
|
||||
select HAVE_GPIO_HARD_PWM if MACH_STM32F1 || MACH_STM32F4 || MACH_STM32G0 || MACH_STM32H7
|
||||
select HAVE_GPIO_HARD_PWM if MACH_STM32F1 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32H7
|
||||
select HAVE_GPIO_BITBANGING if !MACH_STM32F031
|
||||
select HAVE_STRICT_TIMING
|
||||
select HAVE_CHIPID
|
||||
|
|
@ -52,6 +52,9 @@ choice
|
|||
config MACH_STM32F446
|
||||
bool "STM32F446"
|
||||
select MACH_STM32F4
|
||||
config MACH_STM32F765
|
||||
bool "STM32F765"
|
||||
select MACH_STM32F7
|
||||
config MACH_STM32F031
|
||||
bool "STM32F031"
|
||||
select MACH_STM32F0
|
||||
|
|
@ -119,6 +122,8 @@ config MACH_STM32F2
|
|||
bool
|
||||
config MACH_STM32F4
|
||||
bool
|
||||
config MACH_STM32F7
|
||||
bool
|
||||
config MACH_STM32G0
|
||||
bool
|
||||
config MACH_STM32G07x
|
||||
|
|
@ -143,7 +148,7 @@ config HAVE_STM32_USBFS
|
|||
default y if (MACH_STM32F1 || MACH_STM32F070) && !STM32_CLOCK_REF_INTERNAL
|
||||
config HAVE_STM32_USBOTG
|
||||
bool
|
||||
default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32H7
|
||||
default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32H7
|
||||
config HAVE_STM32_CANBUS
|
||||
bool
|
||||
default y if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4x5 || MACH_STM32F446 || MACH_STM32F0x2
|
||||
|
|
@ -170,6 +175,7 @@ config MCU
|
|||
default "stm32f407xx" if MACH_STM32F407
|
||||
default "stm32f429xx" if MACH_STM32F429
|
||||
default "stm32f446xx" if MACH_STM32F446
|
||||
default "stm32f765xx" if MACH_STM32F765
|
||||
default "stm32g070xx" if MACH_STM32G070
|
||||
default "stm32g071xx" if MACH_STM32G071
|
||||
default "stm32g0b0xx" if MACH_STM32G0B0
|
||||
|
|
@ -190,6 +196,7 @@ config CLOCK_FREQ
|
|||
default 84000000 if MACH_STM32F401
|
||||
default 168000000 if MACH_STM32F4x5
|
||||
default 180000000 if MACH_STM32F446
|
||||
default 216000000 if MACH_STM32F765
|
||||
default 64000000 if MACH_STM32G0
|
||||
default 150000000 if MACH_STM32G431
|
||||
default 400000000 if MACH_STM32H7 # 400Mhz is max Klipper currently supports
|
||||
|
|
@ -207,7 +214,7 @@ config FLASH_SIZE
|
|||
default 0x80000 if MACH_STM32F4x5 || MACH_STM32F446
|
||||
default 0x20000 if MACH_STM32G0 || MACH_STM32G431
|
||||
default 0x20000 if MACH_STM32H750
|
||||
default 0x200000 if MACH_STM32H743
|
||||
default 0x200000 if MACH_STM32H743 || MACH_STM32F765
|
||||
default 0x20000 if MACH_N32G45x
|
||||
|
||||
config FLASH_BOOT_ADDRESS
|
||||
|
|
@ -230,6 +237,7 @@ config RAM_SIZE
|
|||
default 0x20000 if MACH_STM32F207
|
||||
default 0x10000 if MACH_STM32F401
|
||||
default 0x20000 if MACH_STM32F4x5 || MACH_STM32F446
|
||||
default 0x80000 if MACH_STM32F765
|
||||
default 0x9000 if MACH_STM32G07x
|
||||
default 0x24000 if MACH_STM32G0Bx
|
||||
default 0x20000 if MACH_STM32H7
|
||||
|
|
@ -254,7 +262,7 @@ config STM32_DFU_ROM_ADDRESS
|
|||
default 0 if !USB
|
||||
default 0x1fffc400 if MACH_STM32F042
|
||||
default 0x1fffc800 if MACH_STM32F072
|
||||
default 0x1fff0000 if MACH_STM32F4 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
|
||||
default 0x1fff0000 if MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
|
||||
default 0x1ff09800 if MACH_STM32H7
|
||||
default 0
|
||||
|
||||
|
|
@ -272,7 +280,7 @@ choice
|
|||
config STM32_FLASH_START_7000
|
||||
bool "28KiB bootloader" if MACH_STM32F1
|
||||
config STM32_FLASH_START_8000
|
||||
bool "32KiB bootloader" if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4
|
||||
bool "32KiB bootloader" if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4 || MACH_STM32F7
|
||||
config STM32_FLASH_START_8800
|
||||
bool "34KiB bootloader (Chitu v6 Bootloader)" if MACH_STM32F103
|
||||
config STM32_FLASH_START_20200
|
||||
|
|
@ -289,7 +297,7 @@ choice
|
|||
config STM32_FLASH_START_4000
|
||||
bool "16KiB bootloader (HID Bootloader)" if MACH_STM32F207 || MACH_STM32F401 || MACH_STM32F4x5 || MACH_STM32F103 || MACH_STM32F072
|
||||
config STM32_FLASH_START_20000
|
||||
bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723
|
||||
bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723 || MACH_STM32F7
|
||||
|
||||
config STM32_FLASH_START_0000
|
||||
bool "No bootloader"
|
||||
|
|
@ -330,6 +338,8 @@ choice
|
|||
bool "16 MHz crystal"
|
||||
config STM32_CLOCK_REF_20M
|
||||
bool "20 MHz crystal"
|
||||
config STM32_CLOCK_REF_24M
|
||||
bool "24 MHz crystal"
|
||||
config STM32_CLOCK_REF_25M
|
||||
bool "25 MHz crystal"
|
||||
config STM32_CLOCK_REF_INTERNAL
|
||||
|
|
@ -338,6 +348,7 @@ endchoice
|
|||
config CLOCK_REF_FREQ
|
||||
int
|
||||
default 25000000 if STM32_CLOCK_REF_25M
|
||||
default 24000000 if STM32_CLOCK_REF_24M
|
||||
default 20000000 if STM32_CLOCK_REF_20M
|
||||
default 16000000 if STM32_CLOCK_REF_16M
|
||||
default 12000000 if STM32_CLOCK_REF_12M
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ dirs-$(CONFIG_MACH_STM32F1) += lib/stm32f1
|
|||
dirs-$(CONFIG_MACH_N32G45x) += lib/n32g45x
|
||||
dirs-$(CONFIG_MACH_STM32F2) += lib/stm32f2
|
||||
dirs-$(CONFIG_MACH_STM32F4) += lib/stm32f4
|
||||
dirs-$(CONFIG_MACH_STM32F7) += lib/stm32f7
|
||||
dirs-$(CONFIG_MACH_STM32G0) += lib/stm32g0
|
||||
dirs-$(CONFIG_MACH_STM32G4) += lib/stm32g4
|
||||
dirs-$(CONFIG_MACH_STM32H7) += lib/stm32h7
|
||||
|
|
@ -23,6 +24,7 @@ CFLAGS-$(CONFIG_MACH_N32G45x) += -mcpu=cortex-m4 -Ilib/n32g45x/include
|
|||
CFLAGS-$(CONFIG_MACH_STM32F1) += -Ilib/stm32f1/include
|
||||
CFLAGS-$(CONFIG_MACH_STM32F2) += -mcpu=cortex-m3 -Ilib/stm32f2/include
|
||||
CFLAGS-$(CONFIG_MACH_STM32F4) += -mcpu=cortex-m4 -Ilib/stm32f4/include
|
||||
CFLAGS-$(CONFIG_MACH_STM32F7) += -mcpu=cortex-m7 -Ilib/stm32f7/include
|
||||
CFLAGS-$(CONFIG_MACH_STM32G0) += -mcpu=cortex-m0plus -Ilib/stm32g0/include
|
||||
CFLAGS-$(CONFIG_MACH_STM32G4) += -mcpu=cortex-m4 -Ilib/stm32g4/include
|
||||
CFLAGS-$(CONFIG_MACH_STM32H7) += -mcpu=cortex-m7 -Ilib/stm32h7/include
|
||||
|
|
@ -52,6 +54,9 @@ src-$(CONFIG_MACH_STM32F2) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
|
|||
src-$(CONFIG_MACH_STM32F4) += ../lib/stm32f4/system_stm32f4xx.c
|
||||
src-$(CONFIG_MACH_STM32F4) += stm32/stm32f4.c generic/armcm_timer.c
|
||||
src-$(CONFIG_MACH_STM32F4) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
|
||||
src-$(CONFIG_MACH_STM32F7) += ../lib/stm32f7/system_stm32f7xx.c
|
||||
src-$(CONFIG_MACH_STM32F7) += stm32/stm32f7.c generic/armcm_timer.c
|
||||
src-$(CONFIG_MACH_STM32F7) += stm32/gpioperiph.c stm32/adc.c stm32/stm32f0_i2c.c
|
||||
src-$(CONFIG_MACH_STM32G0) += generic/timer_irq.c stm32/stm32f0_timer.c
|
||||
src-$(CONFIG_MACH_STM32G0) += stm32/stm32g0.c stm32/gpioperiph.c
|
||||
src-$(CONFIG_MACH_STM32G0) += stm32/stm32f0_adc.c stm32/stm32f0_i2c.c
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ dfu_reboot(void)
|
|||
irq_disable();
|
||||
uint64_t *bflag = (void*)USB_BOOT_FLAG_ADDR;
|
||||
*bflag = USB_BOOT_FLAG;
|
||||
#if CONFIG_MACH_STM32H7
|
||||
#if __CORTEX_M >= 7
|
||||
SCB_CleanDCache_by_Addr((void*)bflag, sizeof(*bflag));
|
||||
#endif
|
||||
NVIC_SystemReset();
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
|
|||
// stm32f0 is ~10Mhz at 50pF
|
||||
// stm32f2 is ~25Mhz at 40pF
|
||||
// stm32f4 is ~50Mhz at 40pF
|
||||
// stm32f7 is ~50Mhz at 40pF
|
||||
// stm32g0 is ~30Mhz at 50pF
|
||||
// stm32h7 is ~85Mhz at 50pF
|
||||
uint32_t ospeed = hs ? 0x03 : (CONFIG_MACH_STM32F0 ? 0x01 : 0x02);
|
||||
|
|
|
|||
|
|
@ -102,6 +102,19 @@ static const struct gpio_pwm_info pwm_regs[] = {
|
|||
{TIM9, GPIO('E', 6), 2, GPIO_FUNCTION(3)},
|
||||
{TIM10, GPIO('B', 8), 1, GPIO_FUNCTION(3)},
|
||||
{TIM11, GPIO('B', 9), 1, GPIO_FUNCTION(3)}
|
||||
#elif CONFIG_MACH_STM32F7
|
||||
{TIM2, GPIO('A', 15), 1, GPIO_FUNCTION(1)},
|
||||
{TIM2, GPIO('B', 3), 2, GPIO_FUNCTION(1)},
|
||||
{TIM2, GPIO('B', 10), 3, GPIO_FUNCTION(1)},
|
||||
{TIM2, GPIO('B', 11), 4, GPIO_FUNCTION(1)},
|
||||
{TIM3, GPIO('B', 4), 1, GPIO_FUNCTION(1)},
|
||||
{TIM3, GPIO('B', 5), 1, GPIO_FUNCTION(1)},
|
||||
{TIM3, GPIO('C', 8), 2, GPIO_FUNCTION(1)},
|
||||
{TIM3, GPIO('C', 9), 2, GPIO_FUNCTION(1)},
|
||||
{TIM5, GPIO('A', 10), 3, GPIO_FUNCTION(1)},
|
||||
{TIM5, GPIO('E', 13), 3, GPIO_FUNCTION(1)},
|
||||
{TIM5, GPIO('A', 11), 4, GPIO_FUNCTION(1)},
|
||||
{TIM5, GPIO('E', 14), 4, GPIO_FUNCTION(1)},
|
||||
#elif CONFIG_MACH_STM32G0
|
||||
{TIM15, GPIO('A', 2), 1, GPIO_FUNCTION(5)},
|
||||
{TIM15, GPIO('A', 3), 2, GPIO_FUNCTION(5)},
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
#include "stm32f2xx.h"
|
||||
#elif CONFIG_MACH_STM32F4
|
||||
#include "stm32f4xx.h"
|
||||
#elif CONFIG_MACH_STM32F7
|
||||
#include "stm32f7xx.h"
|
||||
#elif CONFIG_MACH_STM32G0
|
||||
#include "stm32g0xx.h"
|
||||
#elif CONFIG_MACH_STM32G4
|
||||
|
|
|
|||
|
|
@ -86,9 +86,10 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
|
|||
gpio_peripheral(spi_bus[bus].mosi_pin, spi_bus[bus].function, 0);
|
||||
gpio_peripheral(spi_bus[bus].sck_pin, spi_bus[bus].function, 0);
|
||||
|
||||
// Configure CR2 on stm32 f0/g0/l4/g4
|
||||
#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 \
|
||||
|| CONFIG_MACH_STM32G4
|
||||
// Configure CR2 on stm32 f0/f7/g0/l4/g4
|
||||
#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32F7 || \
|
||||
CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32G4 || \
|
||||
CONFIG_MACH_STM32L4
|
||||
spi->CR2 = SPI_CR2_FRXTH | (7 << SPI_CR2_DS_Pos);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,6 +27,9 @@ struct i2c_info {
|
|||
DECL_CONSTANT_STR("BUS_PINS_i2c1", "PB6,PB7");
|
||||
DECL_ENUMERATION("i2c_bus", "i2c1a", 1);
|
||||
DECL_CONSTANT_STR("BUS_PINS_i2c1a", "PF1,PF0");
|
||||
#elif CONFIG_MACH_STM32F7
|
||||
DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
|
||||
DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
|
||||
#elif CONFIG_MACH_STM32G0
|
||||
DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
|
||||
DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
|
||||
|
|
@ -86,6 +89,8 @@ static const struct i2c_info i2c_bus[] = {
|
|||
{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) },
|
||||
{ I2C1, GPIO('F', 1), GPIO('F', 0), GPIO_FUNCTION(1) },
|
||||
{ I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(1) },
|
||||
#elif CONFIG_MACH_STM32F7
|
||||
{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) },
|
||||
#elif CONFIG_MACH_STM32G0
|
||||
{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(6) },
|
||||
{ I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(6) },
|
||||
|
|
|
|||
|
|
@ -0,0 +1,168 @@
|
|||
// Code to setup clocks on stm32f7
|
||||
//
|
||||
// Copyright (C) 2023 Frederic Morin <frederic.morin.8@gmail.com>
|
||||
//
|
||||
// This file may be distributed under the terms of the GNU GPLv3 license.
|
||||
|
||||
#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
|
||||
#include "board/armcm_boot.h" // VectorTable
|
||||
#include "board/armcm_reset.h" // try_request_canboot
|
||||
#include "board/irq.h" // irq_disable
|
||||
#include "board/misc.h" // bootloader_request
|
||||
#include "command.h" // DECL_CONSTANT_STR
|
||||
#include "internal.h" // enable_pclock
|
||||
#include "sched.h" // sched_main
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Clock setup
|
||||
****************************************************************/
|
||||
|
||||
#define FREQ_PERIPH_DIV 4
|
||||
#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV)
|
||||
#define FREQ_USB 48000000
|
||||
|
||||
// Map a peripheral address to its enable bits
|
||||
struct cline
|
||||
lookup_clock_line(uint32_t periph_base)
|
||||
{
|
||||
if (periph_base >= AHB1PERIPH_BASE) {
|
||||
uint32_t bit = 1 << ((periph_base - AHB1PERIPH_BASE) / 0x400);
|
||||
return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
|
||||
} else if (periph_base >= APB2PERIPH_BASE) {
|
||||
uint32_t bit = 1 << ((periph_base - APB2PERIPH_BASE) / 0x400);
|
||||
if (bit & 0x700)
|
||||
// Skip ADC peripheral reset as they share a bit
|
||||
return (struct cline){.en=&RCC->APB2ENR, .bit=bit};
|
||||
return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
|
||||
} else {
|
||||
uint32_t bit = 1 << ((periph_base - APB1PERIPH_BASE) / 0x400);
|
||||
return (struct cline){.en=&RCC->APB1ENR, .rst=&RCC->APB1RSTR, .bit=bit};
|
||||
}
|
||||
}
|
||||
|
||||
// Return the frequency of the given peripheral clock
|
||||
uint32_t
|
||||
get_pclock_frequency(uint32_t periph_base)
|
||||
{
|
||||
return FREQ_PERIPH;
|
||||
}
|
||||
|
||||
// Enable a GPIO peripheral clock
|
||||
void
|
||||
gpio_clock_enable(GPIO_TypeDef *regs)
|
||||
{
|
||||
uint32_t rcc_pos = ((uint32_t)regs - AHB1PERIPH_BASE) / 0x400;
|
||||
RCC->AHB1ENR |= 1 << rcc_pos;
|
||||
RCC->AHB1ENR;
|
||||
}
|
||||
|
||||
#if !CONFIG_STM32_CLOCK_REF_INTERNAL
|
||||
DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
|
||||
#endif
|
||||
|
||||
// Main clock setup called at chip startup
|
||||
static void
|
||||
clock_setup(void)
|
||||
{
|
||||
// Configure and enable PLL
|
||||
const uint32_t pll_base = 2000000, pll_freq = CONFIG_CLOCK_FREQ * 2;
|
||||
uint32_t pllcfgr;
|
||||
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
|
||||
// Configure 216Mhz PLL from external crystal (HSE)
|
||||
const uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos);
|
||||
} else {
|
||||
// Configure 216Mhz PLL from internal 16Mhz oscillator (HSI)
|
||||
const uint32_t div = 16000000 / pll_base;
|
||||
pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
|
||||
}
|
||||
RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos)
|
||||
| (0 << RCC_PLLCFGR_PLLP_Pos) // /2
|
||||
| ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos)
|
||||
| (2 << RCC_PLLCFGR_PLLR_Pos));
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
// Enable "over drive"
|
||||
enable_pclock(PWR_BASE);
|
||||
PWR->CR1 = (3 << PWR_CR1_VOS_Pos) | PWR_CR1_ODEN;
|
||||
while (!(PWR->CSR1 & PWR_CSR1_ODRDY))
|
||||
;
|
||||
PWR->CR1 = (3 << PWR_CR1_VOS_Pos) | PWR_CR1_ODEN | PWR_CR1_ODSWEN;
|
||||
while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))
|
||||
;
|
||||
|
||||
// Enable 48Mhz USB clock
|
||||
if (CONFIG_USB) {
|
||||
// setup PLLSAI
|
||||
const uint32_t plls_base = 2000000, plls_freq = FREQ_USB * 4;
|
||||
RCC->PLLSAICFGR = (
|
||||
((plls_freq/plls_base) << RCC_PLLSAICFGR_PLLSAIN_Pos) // *96
|
||||
| (((plls_freq/FREQ_USB)/2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)// /4
|
||||
| ((plls_freq/FREQ_USB) << RCC_PLLSAICFGR_PLLSAIQ_Pos));
|
||||
// enable PLLSAI and wait for PLLSAI lock
|
||||
RCC->CR |= RCC_CR_PLLSAION;
|
||||
while (!(RCC->CR & RCC_CR_PLLSAIRDY))
|
||||
;
|
||||
// set CLK48 source to PLLSAI
|
||||
RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL; // RCC_CLK48SOURCE_PLLSAIP
|
||||
}
|
||||
|
||||
// Set flash latency
|
||||
MODIFY_REG(
|
||||
FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_ACR_LATENCY_7WS));
|
||||
|
||||
// Wait for PLL lock
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
;
|
||||
|
||||
// Switch system clock to PLL
|
||||
RCC->CFGR = RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4 | RCC_CFGR_SW_PLL;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Bootloader
|
||||
****************************************************************/
|
||||
|
||||
// Handle reboot requests
|
||||
void
|
||||
bootloader_request(void)
|
||||
{
|
||||
try_request_canboot();
|
||||
dfu_reboot();
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Startup
|
||||
****************************************************************/
|
||||
|
||||
// Main entry point - called from armcm_boot.c:ResetHandler()
|
||||
void
|
||||
armcm_main(void)
|
||||
{
|
||||
// Run SystemInit() and then restore VTOR
|
||||
SystemInit();
|
||||
SCB->VTOR = (uint32_t)VectorTable;
|
||||
|
||||
// Reset peripheral clocks (for some bootloaders that don't)
|
||||
RCC->AHB1ENR = 0x00100000;
|
||||
RCC->AHB2ENR = 0x00000000;
|
||||
RCC->AHB3ENR = 0x00000000;
|
||||
RCC->APB1ENR = 0x00000400;
|
||||
RCC->APB2ENR = 0x00000000;
|
||||
|
||||
dfu_reboot_check();
|
||||
|
||||
// STM32F7 specific DWT unlock required prior to timer_init() DWT setup.
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
DWT->LAR = 0xC5ACCE55;
|
||||
|
||||
clock_setup();
|
||||
|
||||
sched_main();
|
||||
}
|
||||
|
|
@ -426,7 +426,7 @@ usb_init(void)
|
|||
OTG->GUSBCFG = (USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL
|
||||
| (6 << USB_OTG_GUSBCFG_TRDT_Pos));
|
||||
OTGD->DCFG |= (3 << USB_OTG_DCFG_DSPD_Pos);
|
||||
#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7
|
||||
#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32F7
|
||||
OTG->GOTGCTL = USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
|
||||
#else
|
||||
OTG->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
# Base config file for STM32F765 ARM processor
|
||||
CONFIG_MACH_STM32=y
|
||||
CONFIG_MACH_STM32F765=y
|
||||
Loading…
Reference in New Issue