stm32: Add new gpioperiph.c file for gpio_peripheral() code
The gpio_peripheral() code is the same in stm32f0.c, stm32f4.c, and stm32h7.c. Move that function to a new gpioperiph.c file to avoid code duplication. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Kevin O'Connor
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debcc22fc5
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2ee1f48895
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@ -29,20 +29,20 @@ src-y += stm32/watchdog.c stm32/gpio.c generic/crc16_ccitt.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-$(CONFIG_MACH_STM32F0) += ../lib/stm32f0/system_stm32f0xx.c
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src-$(CONFIG_MACH_STM32F0) += generic/timer_irq.c stm32/stm32f0_timer.c
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src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0.c stm32/stm32f0_adc.c
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src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0_i2c.c
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src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0.c stm32/gpioperiph.c
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src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0_adc.c stm32/stm32f0_i2c.c
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src-$(CONFIG_MACH_STM32F1) += ../lib/stm32f1/system_stm32f1xx.c
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src-$(CONFIG_MACH_STM32F1) += stm32/stm32f1.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32F1) += stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32F2) += ../lib/stm32f2/system_stm32f2xx.c
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src-$(CONFIG_MACH_STM32F2) += stm32/stm32f4.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32F2) += stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32F2) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32F4) += ../lib/stm32f4/system_stm32f4xx.c
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src-$(CONFIG_MACH_STM32F4) += stm32/stm32f4.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32F4) += stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32F4) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32H7) += ../lib/stm32h7/system_stm32h7xx.c
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src-$(CONFIG_MACH_STM32H7) += stm32/stm32h7.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32H7) += stm32/stm32h7_adc.c
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src-$(CONFIG_MACH_STM32H7) += stm32/gpioperiph.c stm32/stm32h7_adc.c
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spi-src-y := stm32/spi.c
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spi-src-$(CONFIG_MACH_STM32H7) := stm32/stm32h7_spi.c
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src-$(CONFIG_HAVE_GPIO_SPI) += $(spi-src-y)
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@ -0,0 +1,37 @@
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// Code to setup gpio on stm32 chip (except for stm32f1)
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//
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// Copyright (C) 2019-2021 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "internal.h" // gpio_peripheral
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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gpio_clock_enable(regs);
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// Configure GPIO
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uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos);
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// Setup OSPEEDR:
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// stm32f0 is ~10Mhz at 50pF
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// stm32f2 is ~25Mhz at 40pF
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// stm32f4 is ~50Mhz at 40pF
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// stm32h7 is ~85Mhz at 50pF
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uint32_t ospeed = CONFIG_MACH_STM32F0 ? 0x01 : 0x02;
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (ospeed << m_shift);
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}
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@ -1,4 +1,4 @@
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// Code to setup clocks and gpio on stm32f0
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// Code to setup clocks on stm32f0
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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@ -64,31 +64,6 @@ gpio_clock_enable(GPIO_TypeDef *regs)
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RCC->AHBENR;
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}
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#define STM_OSPEED 0x1 // ~10Mhz at 50pF
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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gpio_clock_enable(regs);
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// Configure GPIO
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uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (STM_OSPEED << m_shift);
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}
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#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 1024)
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#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT"
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@ -1,4 +1,4 @@
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// Code to setup clocks and gpio on stm32f2/stm32f4
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// Code to setup clocks on stm32f2/stm32f4
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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@ -75,31 +75,6 @@ gpio_clock_enable(GPIO_TypeDef *regs)
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RCC->AHB1ENR;
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}
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#define STM_OSPEED 0x2 // ~50Mhz at 40pF on STM32F4 (~25Mhz at 40pF on STM32F2)
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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gpio_clock_enable(regs);
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// Configure GPIO
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uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (STM_OSPEED << m_shift);
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}
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#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 4096)
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#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT"
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@ -1,4 +1,4 @@
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// Code to setup clocks and gpio on stm32h7
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// Code to setup clocks on stm32h7
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//
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// Copyright (C) 2020 Konstantin Vogel <konstantin.vogel@gmx.net>
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//
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@ -102,31 +102,6 @@ gpio_clock_enable(GPIO_TypeDef *regs)
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enable_pclock((uint32_t)regs);
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}
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#define STM_OSPEED 0x2 // ~85Mhz at 50pF
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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gpio_clock_enable(regs);
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// Configure GPIO
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uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (STM_OSPEED << m_shift);
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}
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#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 4096)
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#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT"
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