stm32: Initial support for stm32f070
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
7e090a996a
commit
2c535106ee
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@ -6,8 +6,8 @@ config STM32_SELECT
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bool
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default y
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select HAVE_GPIO
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select HAVE_GPIO_ADC
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select HAVE_GPIO_I2C
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select HAVE_GPIO_ADC if !MACH_STM32F0
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select HAVE_GPIO_I2C if !MACH_STM32F0
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select HAVE_GPIO_SPI
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select HAVE_GPIO_BITBANGING
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@ -29,15 +29,20 @@ choice
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config MACH_STM32F446
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bool "STM32F446"
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select MACH_STM32F4
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config MACH_STM32F070
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bool "STM32F070"
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select MACH_STM32F0
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endchoice
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config MACH_STM32F0
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bool
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config MACH_STM32F1
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bool
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config MACH_STM32F4
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bool
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config HAVE_STM32_USBFS
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bool
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default y if MACH_STM32F103
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default y if MACH_STM32F103 || MACH_STM32F0
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default n
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config HAVE_STM32_USBOTG
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bool
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@ -46,6 +51,7 @@ config HAVE_STM32_USBOTG
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config MCU
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string
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default "stm32f070xb" if MACH_STM32F070
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default "stm32f103xe" if MACH_STM32F103
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default "stm32f405xx" if MACH_STM32F405
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default "stm32f407xx" if MACH_STM32F407
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@ -53,12 +59,14 @@ config MCU
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config CLOCK_FREQ
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int
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default 48000000 if MACH_STM32F0
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default 72000000 if MACH_STM32F103
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default 168000000 if MACH_STM32F405 || MACH_STM32F407
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default 180000000 if MACH_STM32F446
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config FLASH_SIZE
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hex
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default 0x20000 if MACH_STM32F070
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default 0x10000 if MACH_STM32F103
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default 0x80000 if MACH_STM32F4
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@ -68,6 +76,7 @@ config RAM_START
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config RAM_SIZE
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hex
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default 0x4000 if MACH_STM32F070
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default 0x5000 if MACH_STM32F103
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default 0x20000 if MACH_STM32F4
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@ -4,12 +4,14 @@
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CROSS_PREFIX=arm-none-eabi-
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dirs-y += src/stm32 src/generic
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dirs-$(CONFIG_MACH_STM32F0) += lib/stm32f0
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dirs-$(CONFIG_MACH_STM32F1) += lib/stm32f1
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dirs-$(CONFIG_MACH_STM32F4) += lib/stm32f4
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MCU := $(shell echo $(CONFIG_MCU))
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MCU_UPPER := $(shell echo $(CONFIG_MCU) | tr a-z A-Z | tr X x)
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CFLAGS-$(CONFIG_MACH_STM32F0) += -mcpu=cortex-m0 -Ilib/stm32f0/include
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CFLAGS-$(CONFIG_MACH_STM32F1) += -mcpu=cortex-m3 -Ilib/stm32f1/include
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CFLAGS-$(CONFIG_MACH_STM32F4) += -mcpu=cortex-m4 -Ilib/stm32f4/include
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CFLAGS-$(CONFIG_MACH_STM32F4) += -mfpu=fpv4-sp-d16 -mfloat-abi=hard
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@ -21,19 +23,23 @@ $(OUT)klipper.elf: $(OUT)src/generic/armcm_link.ld
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# Add source files
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src-y += stm32/main.c stm32/watchdog.c stm32/gpio.c generic/crc16_ccitt.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_timer.c
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src-y += generic/armcm_reset.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-$(CONFIG_MACH_STM32F0) += ../lib/stm32f0/system_stm32f0xx.c
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src-$(CONFIG_MACH_STM32F0) += generic/timer_irq.c stm32/stm32f0_timer.c
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src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0.c
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src-$(CONFIG_MACH_STM32F1) += ../lib/stm32f1/system_stm32f1xx.c
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src-$(CONFIG_MACH_STM32F1) += stm32/stm32f1.c
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src-$(CONFIG_MACH_STM32F1) += stm32/stm32f1.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32F4) += ../lib/stm32f4/system_stm32f4xx.c
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src-$(CONFIG_MACH_STM32F4) += stm32/stm32f4.c
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src-$(CONFIG_MACH_STM32F4) += stm32/stm32f4.c generic/armcm_timer.c
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src-$(CONFIG_HAVE_GPIO_ADC) += stm32/adc.c
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src-$(CONFIG_HAVE_GPIO_I2C) += stm32/i2c.c
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src-$(CONFIG_HAVE_GPIO_SPI) += stm32/spi.c
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usb-src-$(CONFIG_HAVE_STM32_USBFS) := stm32/usbfs.c
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usb-src-$(CONFIG_HAVE_STM32_USBOTG) := stm32/usbotg.c
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src-$(CONFIG_USBSERIAL) += $(usb-src-y) generic/usb_cdc.c
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src-$(CONFIG_SERIAL) += stm32/serial.c generic/serial_irq.c
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serial-src-y := stm32/serial.c
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serial-src-$(CONFIG_MACH_STM32F0) := stm32/stm32f0_serial.c
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src-$(CONFIG_SERIAL) += $(serial-src-y) generic/serial_irq.c
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# Binary output file rules
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target-y += $(OUT)klipper.bin
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@ -15,9 +15,13 @@ DECL_ENUMERATION_RANGE("pin", "PA0", GPIO('A', 0), 16);
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DECL_ENUMERATION_RANGE("pin", "PB0", GPIO('B', 0), 16);
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DECL_ENUMERATION_RANGE("pin", "PC0", GPIO('C', 0), 16);
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DECL_ENUMERATION_RANGE("pin", "PD0", GPIO('D', 0), 16);
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#ifdef GPIOE
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DECL_ENUMERATION_RANGE("pin", "PE0", GPIO('E', 0), 16);
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#ifdef GPIOH
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#endif
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#ifdef GPIOF
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DECL_ENUMERATION_RANGE("pin", "PF0", GPIO('F', 0), 16);
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#endif
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#ifdef GPIOH
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DECL_ENUMERATION_RANGE("pin", "PG0", GPIO('G', 0), 16);
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DECL_ENUMERATION_RANGE("pin", "PH0", GPIO('H', 0), 16);
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#endif
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@ -26,9 +30,15 @@ DECL_ENUMERATION_RANGE("pin", "PI0", GPIO('I', 0), 16);
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#endif
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GPIO_TypeDef * const digital_regs[] = {
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['A' - 'A'] = GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
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['A' - 'A'] = GPIOA, GPIOB, GPIOC, GPIOD,
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#ifdef GPIOE
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['E' - 'A'] = GPIOE,
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#endif
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#ifdef GPIOF
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['F' - 'A'] = GPIOF,
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#endif
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#ifdef GPIOH
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['F' - 'A'] = GPIOF, GPIOG, GPIOH,
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['G' - 'A'] = GPIOG, GPIOH,
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#endif
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#ifdef GPIOI
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['I' - 'A'] = GPIOI,
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@ -4,9 +4,11 @@
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#include "autoconf.h" // CONFIG_MACH_STM32F1
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#if CONFIG_MACH_STM32F1
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#if CONFIG_MACH_STM32F0
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#include "stm32f0xx.h"
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#elif CONFIG_MACH_STM32F1
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#include "stm32f1xx.h"
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#else
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#elif CONFIG_MACH_STM32F4
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#include "stm32f4xx.h"
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#endif
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@ -27,9 +27,11 @@ DECL_CONSTANT_STR("BUS_PINS_spi3a", "PC11,PC12,PC10");
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#endif
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#endif
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#define SPI_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32F0 ? 0 : 5)
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static const struct spi_info spi_bus[] = {
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{ SPI2, GPIO('B', 14), GPIO('B', 15), GPIO('B', 13), GPIO_FUNCTION(5) },
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{ SPI1, GPIO('A', 6), GPIO('A', 7), GPIO('A', 5), GPIO_FUNCTION(5) },
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{ SPI2, GPIO('B', 14), GPIO('B', 15), GPIO('B', 13), SPI_FUNCTION },
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{ SPI1, GPIO('A', 6), GPIO('A', 7), GPIO('A', 5), SPI_FUNCTION },
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#ifdef SPI3
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{ SPI3, GPIO('B', 4), GPIO('B', 5), GPIO('B', 3), GPIO_FUNCTION(6) },
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#if CONFIG_MACH_STM32F4
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@ -0,0 +1,136 @@
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// Code to setup clocks and gpio on stm32f0
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_8M
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#define FREQ_PERIPH 48000000
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// Enable a peripheral clock
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void
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enable_pclock(uint32_t periph_base)
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{
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if (periph_base < SYSCFG_BASE) {
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uint32_t pos = (periph_base - APBPERIPH_BASE) / 0x400;
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RCC->APB1ENR |= 1 << pos;
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RCC->APB1ENR;
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} else if (periph_base < AHBPERIPH_BASE) {
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uint32_t pos = (periph_base - SYSCFG_BASE) / 0x400;
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RCC->APB2ENR |= 1 << pos;
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RCC->APB2ENR;
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} else {
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uint32_t pos = (periph_base - AHB2PERIPH_BASE) / 0x400;
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RCC->AHBENR |= 1 << (pos + 17);
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RCC->AHBENR;
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}
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}
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// Check if a peripheral clock has been enabled
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int
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is_enabled_pclock(uint32_t periph_base)
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{
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if (periph_base < SYSCFG_BASE) {
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uint32_t pos = (periph_base - APBPERIPH_BASE) / 0x400;
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return RCC->APB1ENR & (1 << pos);
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} else if (periph_base < AHBPERIPH_BASE) {
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uint32_t pos = (periph_base - SYSCFG_BASE) / 0x400;
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return RCC->APB2ENR & (1 << pos);
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} else {
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uint32_t pos = (periph_base - AHB2PERIPH_BASE) / 0x400;
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return RCC->AHBENR & (1 << (pos + 17));
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Enable a GPIO peripheral clock
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void
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gpio_clock_enable(GPIO_TypeDef *regs)
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{
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uint32_t rcc_pos = ((uint32_t)regs - AHB2PERIPH_BASE) / 0x400;
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RCC->AHBENR |= 1 << (rcc_pos + 17);
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RCC->AHBENR;
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}
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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gpio_clock_enable(regs);
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// Configure GPIO
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uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift);
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}
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// Handle USB reboot requests
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void
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usb_request_bootloader(void)
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{
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}
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#if CONFIG_CLOCK_REF_8M
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1");
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#endif
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// Configure and enable the PLL as clock source
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static void
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pll_setup(void)
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{
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uint32_t cfgr;
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if (CONFIG_CLOCK_REF_8M) {
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// Configure 48Mhz PLL from external 8Mhz crystal (HSE)
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RCC->CR |= RCC_CR_HSEON;
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cfgr = RCC_CFGR_PLLSRC_HSE_PREDIV | ((6 - 2) << RCC_CFGR_PLLMUL_Pos);
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} else {
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// Configure 48Mhz PLL from internal 8Mhz oscillator (HSI)
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cfgr = RCC_CFGR_PLLSRC_HSI_DIV2 | ((12 - 2) << RCC_CFGR_PLLMUL_Pos);
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}
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RCC->CFGR = cfgr;
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RCC->CR |= RCC_CR_PLLON;
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// Wait for PLL lock
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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// Switch system clock to PLL
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RCC->CFGR = cfgr | RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
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;
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// Select PLL as source for USB clock
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if (CONFIG_USBSERIAL)
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RCC->CFGR3 = RCC_CFGR3_USBSW;
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}
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// Main clock setup called at chip startup
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void
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clock_setup(void)
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{
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// Set flash latency
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FLASH->ACR = (1 << FLASH_ACR_LATENCY_Pos) | FLASH_ACR_PRFTBE;
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// Configure main clock
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pll_setup();
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}
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@ -0,0 +1,69 @@
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// STM32F0 serial
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_SERIAL_BAUD
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#include "board/armcm_boot.h" // armcm_enable_irq
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#include "board/serial_irq.h" // serial_rx_byte
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#include "sched.h" // DECL_INIT
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// Select the configured serial port
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#if CONFIG_SERIAL_PORT == 1
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA10,PA9");
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#define GPIO_Rx GPIO('A', 10)
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#define GPIO_Tx GPIO('A', 9)
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#define USARTx USART1
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#define USARTx_IRQn USART1_IRQn
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#elif CONFIG_SERIAL_PORT == 2
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2");
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#define GPIO_Rx GPIO('A', 3)
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#define GPIO_Tx GPIO('A', 2)
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#define USARTx USART2
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#define USARTx_IRQn USART2_IRQn
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#endif
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#define CR1_FLAGS (USART_CR1_UE | USART_CR1_RE | USART_CR1_TE \
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| USART_CR1_RXNEIE)
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void
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USARTx_IRQHandler(void)
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{
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uint32_t sr = USARTx->ISR;
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if (sr & (USART_ISR_RXNE | USART_ISR_ORE))
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serial_rx_byte(USARTx->RDR);
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if (sr & USART_ISR_TXE && USARTx->CR1 & USART_CR1_TXEIE) {
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uint8_t data;
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int ret = serial_get_tx_byte(&data);
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if (ret)
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USARTx->CR1 = CR1_FLAGS;
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else
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USARTx->TDR = data;
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}
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}
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void
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serial_enable_tx_irq(void)
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{
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USARTx->CR1 = CR1_FLAGS | USART_CR1_TXEIE;
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}
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void
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serial_init(void)
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{
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enable_pclock((uint32_t)USARTx);
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uint32_t pclk = get_pclock_frequency((uint32_t)USARTx);
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uint32_t div = DIV_ROUND_CLOSEST(pclk, CONFIG_SERIAL_BAUD);
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USARTx->BRR = (((div / 16) << USART_BRR_DIV_MANTISSA_Pos)
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| ((div % 16) << USART_BRR_DIV_FRACTION_Pos));
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USARTx->CR1 = CR1_FLAGS;
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armcm_enable_irq(USARTx_IRQHandler, USARTx_IRQn, 0);
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gpio_peripheral(GPIO_Rx, GPIO_FUNCTION(1), 1);
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gpio_peripheral(GPIO_Tx, GPIO_FUNCTION(1), 0);
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}
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DECL_INIT(serial_init);
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@ -0,0 +1,124 @@
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// STM32F0 timer support
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/armcm_boot.h" // armcm_enable_irq
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#include "board/armcm_timer.h" // udelay
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#include "board/internal.h" // TIM3
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#include "board/io.h" // readl
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#include "board/irq.h" // irq_disable
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#include "board/misc.h" // timer_read_time
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#include "sched.h" // DECL_INIT
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#include "command.h" // DECL_SHUTDOWN
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#include "board/timer_irq.h" // timer_dispatch_many
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/****************************************************************
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* Low level timer code
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****************************************************************/
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// Use 32bit TIM2 timer if available (otherwise use 16bit TIM3 timer)
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#ifdef TIM2
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#define TIMx TIM2
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||||
#define TIMx_IRQn TIM2_IRQn
|
||||
#define HAVE_TIMER_32BIT 1
|
||||
#else
|
||||
#define TIMx TIM3
|
||||
#define TIMx_IRQn TIM3_IRQn
|
||||
#define HAVE_TIMER_32BIT 0
|
||||
#endif
|
||||
|
||||
static inline uint32_t
|
||||
timer_get(void)
|
||||
{
|
||||
return TIMx->CNT;
|
||||
}
|
||||
|
||||
static inline void
|
||||
timer_set(uint32_t next)
|
||||
{
|
||||
TIMx->CCR1 = next;
|
||||
TIMx->SR = 0;
|
||||
}
|
||||
|
||||
// Activate timer dispatch as soon as possible
|
||||
void
|
||||
timer_kick(void)
|
||||
{
|
||||
timer_set(timer_get() + 50);
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* 16bit hardware timer to 32bit conversion
|
||||
****************************************************************/
|
||||
|
||||
// High bits of timer (top 17 bits)
|
||||
static uint32_t timer_high;
|
||||
|
||||
// Return the current time (in absolute clock ticks).
|
||||
uint32_t __always_inline
|
||||
timer_read_time(void)
|
||||
{
|
||||
if (HAVE_TIMER_32BIT)
|
||||
return timer_get();
|
||||
uint32_t th = readl(&timer_high);
|
||||
uint32_t cur = timer_get();
|
||||
// Combine timer_high (high 17 bits) and current time (low 16
|
||||
// bits) using method that handles rollovers correctly.
|
||||
return (th ^ cur) + (th & 0xffff);
|
||||
}
|
||||
|
||||
// Update timer_high every 0x8000 clock ticks
|
||||
static uint_fast8_t
|
||||
timer_event(struct timer *t)
|
||||
{
|
||||
timer_high += 0x8000;
|
||||
t->waketime = timer_high + 0x8000;
|
||||
return SF_RESCHEDULE;
|
||||
}
|
||||
static struct timer wrap_timer = {
|
||||
.func = timer_event,
|
||||
.waketime = 0x8000,
|
||||
};
|
||||
|
||||
void
|
||||
timer_reset(void)
|
||||
{
|
||||
if (!HAVE_TIMER_32BIT)
|
||||
sched_add_timer(&wrap_timer);
|
||||
}
|
||||
DECL_SHUTDOWN(timer_reset);
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Setup and irqs
|
||||
****************************************************************/
|
||||
|
||||
// Hardware timer IRQ handler - dispatch software timers
|
||||
void __aligned(16)
|
||||
TIMx_IRQHandler(void)
|
||||
{
|
||||
irq_disable();
|
||||
uint32_t next = timer_dispatch_many();
|
||||
timer_set(next);
|
||||
irq_enable();
|
||||
}
|
||||
|
||||
void
|
||||
timer_init(void)
|
||||
{
|
||||
irqstatus_t flag = irq_save();
|
||||
enable_pclock((uint32_t)TIMx);
|
||||
TIMx->CNT = 0;
|
||||
TIMx->DIER = TIM_DIER_CC1IE;
|
||||
TIMx->CCER = TIM_CCER_CC1E;
|
||||
armcm_enable_irq(TIMx_IRQHandler, TIMx_IRQn, 2);
|
||||
timer_kick();
|
||||
timer_reset();
|
||||
TIMx->CR1 = TIM_CR1_CEN;
|
||||
irq_restore(flag);
|
||||
}
|
||||
DECL_INIT(timer_init);
|
||||
|
|
@ -235,7 +235,7 @@ usb_reset(void)
|
|||
|
||||
// Main irq handler
|
||||
void
|
||||
USB_LP_CAN1_RX0_IRQHandler(void)
|
||||
USB_IRQHandler(void)
|
||||
{
|
||||
uint32_t istr = USB->ISTR;
|
||||
if (istr & USB_ISTR_CTR) {
|
||||
|
|
@ -269,10 +269,12 @@ DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12");
|
|||
void
|
||||
usb_init(void)
|
||||
{
|
||||
if (CONFIG_MACH_STM32F1) {
|
||||
// Pull the D+ pin low briefly to signal a new connection
|
||||
gpio_out_setup(GPIO('A', 12), 0);
|
||||
udelay(5000);
|
||||
gpio_in_setup(GPIO('A', 12), 0);
|
||||
}
|
||||
|
||||
// Enable USB clock
|
||||
enable_pclock(USB_BASE);
|
||||
|
|
@ -280,12 +282,21 @@ usb_init(void)
|
|||
// Setup USB packet memory
|
||||
btable_configure();
|
||||
|
||||
// Enable USB pullup
|
||||
#ifdef USB_BCDR_DPPU
|
||||
USB->BCDR = USB_BCDR_DPPU;
|
||||
#endif
|
||||
|
||||
// Reset usb controller and enable interrupts
|
||||
USB->CNTR = USB_CNTR_FRES;
|
||||
USB->BTABLE = 0;
|
||||
USB->DADDR = 0;
|
||||
USB->CNTR = USB_CNTR_RESETM;
|
||||
USB->ISTR = 0;
|
||||
armcm_enable_irq(USB_LP_CAN1_RX0_IRQHandler, USB_LP_CAN1_RX0_IRQn, 1);
|
||||
#if CONFIG_MACH_STM32F103
|
||||
armcm_enable_irq(USB_IRQHandler, USB_LP_IRQn, 1);
|
||||
#elif CONFIG_MACH_STM32F0
|
||||
armcm_enable_irq(USB_IRQHandler, USB_IRQn, 1);
|
||||
#endif
|
||||
}
|
||||
DECL_INIT(usb_init);
|
||||
|
|
|
|||
Loading…
Reference in New Issue