diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c
index 8656495b..e6f8637f 100644
--- a/src/stm32/stm32f4.c
+++ b/src/stm32/stm32f4.c
@@ -145,7 +145,8 @@ enable_clock_stm32f40x(void)
 {
 #if CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407 \
     || CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F429
-    uint32_t pll_base = 2000000, pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
+    uint32_t pll_base = (CONFIG_STM32_CLOCK_REF_25M) ? 1000000 : 2000000;
+    uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
     if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
         // Configure 168Mhz PLL from external crystal (HSE)
         uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;