From 147492b25357e486bea35fbeb57405dcc47e53aa Mon Sep 17 00:00:00 2001 From: Alex Maclean Date: Fri, 15 Dec 2023 22:49:07 +0000 Subject: [PATCH] stm32: Fix ADC for STM32G4 At least STM32G4 requires four ADC clock cycles between hardware clearing ADCCAL and setting ADEN or the write disappears. Make a tenacious write attempt. Signed-off-by: Alex Maclean --- src/stm32/stm32h7_adc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/stm32/stm32h7_adc.c b/src/stm32/stm32h7_adc.c index 57d4b15c..e9dc8f84 100644 --- a/src/stm32/stm32h7_adc.c +++ b/src/stm32/stm32h7_adc.c @@ -240,9 +240,10 @@ gpio_adc_setup(uint32_t pin) // Enable ADC adc->ISR = ADC_ISR_ADRDY; adc->ISR; // Dummy read to make sure write is flushed - adc->CR |= ADC_CR_ADEN; + while (!(adc->CR & ADC_CR_ADEN)) + adc->CR |= ADC_CR_ADEN; while (!(adc->ISR & ADC_ISR_ADRDY)) - ; + ; // Set ADC clock cycles sample time for every channel uint32_t av = (aticks | (aticks << 3) | (aticks << 6)