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stm32: Fix ADC for STM32G4 

At least STM32G4 requires four ADC clock cycles between hardware
clearing ADCCAL and setting ADEN or the write disappears. Make a
tenacious write attempt.

Signed-off-by: Alex Maclean <monkeh@monkeh.net>
This commit is contained in:
Alex Maclean 2023-12-15 22:49:07 +00:00 committed by KevinOConnor
parent 71ab6240f2
commit 147492b253
1 changed files with 3 additions and 2 deletions
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5
src/stm32/stm32h7_adc.c
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@ -240,9 +240,10 @@ gpio_adc_setup(uint32_t pin)
// Enable ADC
adc->ISR = ADC_ISR_ADRDY;
adc->ISR; // Dummy read to make sure write is flushed
adc->CR |= ADC_CR_ADEN;
while (!(adc->CR & ADC_CR_ADEN))
adc->CR |= ADC_CR_ADEN;
while (!(adc->ISR & ADC_ISR_ADRDY))
;
;
// Set ADC clock cycles sample time for every channel
uint32_t av = (aticks | (aticks << 3) | (aticks << 6)