stm32: Simplify setting of adc_common fields in stm32h7_adc.c
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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@ -18,7 +18,6 @@
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#define RCC_AHBENR_ADCEN (RCC_AHB1ENR_ADC12EN)
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#define ADC_CKMODE (0b11)
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#define ADC_ATICKS (0b101)
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#define ADC_TS (ADC3_COMMON)
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#if CONFIG_MACH_STM32H723
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#define PCSEL PCSEL_RES0
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#endif
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@ -27,13 +26,11 @@
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#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADCEN)
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#define ADC_CKMODE (0)
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#define ADC_ATICKS (0b100)
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#define ADC_TS (ADC12_COMMON)
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#elif CONFIG_MACH_STM32G4
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#define RCC_AHBENR_ADC (RCC->AHB2ENR)
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#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADC12EN)
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#define ADC_CKMODE (0b11)
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#define ADC_ATICKS (0b100)
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#define ADC_TS (ADC12_COMMON)
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#define ADC_CCR_TSEN (ADC_CCR_VSENSESEL)
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#endif
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@ -199,32 +196,32 @@ gpio_adc_setup(uint32_t pin)
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// (SYSCLK 480Mhz) /HPRE(2) /CKMODE divider(4) /additional divider(2)
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// (ADC clock 30Mhz)
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ADC_TypeDef *adc;
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ADC_Common_TypeDef *adc_common;
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#ifdef ADC3
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if (chan >= 2 * ADCIN_BANK_SIZE){
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chan -= 2 * ADCIN_BANK_SIZE;
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adc = ADC3;
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adc_common = ADC3_COMMON;
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if (!is_enabled_pclock(ADC3_BASE)) {
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enable_pclock(ADC3_BASE);
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}
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MODIFY_REG(ADC3_COMMON->CCR, ADC_CCR_CKMODE_Msk,
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ADC_CKMODE << ADC_CCR_CKMODE_Pos);
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chan -= 2 * ADCIN_BANK_SIZE;
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} else
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#endif
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#ifdef ADC2
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if (chan >= ADCIN_BANK_SIZE){
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adc = ADC2;
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RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN;
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MODIFY_REG(ADC12_COMMON->CCR, ADC_CCR_CKMODE_Msk,
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ADC_CKMODE << ADC_CCR_CKMODE_Pos);
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chan -= ADCIN_BANK_SIZE;
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adc = ADC2;
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adc_common = ADC12_COMMON;
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RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN;
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} else
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#endif
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{
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adc = ADC1;
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adc_common = ADC12_COMMON;
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RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN;
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MODIFY_REG(ADC12_COMMON->CCR, ADC_CCR_CKMODE_Msk,
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ADC_CKMODE << ADC_CCR_CKMODE_Pos);
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}
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MODIFY_REG(adc_common->CCR, ADC_CCR_CKMODE_Msk,
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ADC_CKMODE << ADC_CCR_CKMODE_Pos);
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// Enable the ADC
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if (!(adc->CR & ADC_CR_ADEN)) {
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@ -285,7 +282,7 @@ gpio_adc_setup(uint32_t pin)
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}
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if (pin == ADC_TEMPERATURE_PIN) {
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ADC_TS->CCR |= ADC_CCR_TSEN;
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adc_common->CCR |= ADC_CCR_TSEN;
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} else {
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gpio_peripheral(pin, GPIO_ANALOG, 0);
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}
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