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stm32: Use a consistent bank size of 20 across all chips in stm32h7_adc.c 

Add a pad entry to adc_pins[] on stm32l4 so that it matches the other
chips.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2022-12-13 11:52:08 -05:00
parent f571618376
commit 0bf073ba08
1 changed files with 3 additions and 3 deletions
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6
src/stm32/stm32h7_adc.c
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@ -14,7 +14,6 @@
#include "sched.h" // sched_shutdown
#if CONFIG_MACH_STM32H7
#define ADCIN_BANK_SIZE (20)
#define RCC_AHBENR_ADC (RCC->AHB1ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB1ENR_ADC12EN)
#define ADC_CKMODE (0b11)
@ -24,14 +23,12 @@
#define PCSEL PCSEL_RES0
#endif
#elif CONFIG_MACH_STM32L4
#define ADCIN_BANK_SIZE (19)
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADCEN)
#define ADC_CKMODE (0)
#define ADC_ATICKS (0b100)
#define ADC_TS (ADC12_COMMON)
#elif CONFIG_MACH_STM32G4
#define ADCIN_BANK_SIZE (19)
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADC12EN)
#define ADC_CKMODE (0b11)
@ -45,6 +42,8 @@ DECL_ENUMERATION("pin", "ADC_TEMPERATURE", ADC_TEMPERATURE_PIN);
DECL_CONSTANT("ADC_MAX", 4095);
#define ADCIN_BANK_SIZE 20
// GPIOs like A0_C are not covered!
// This always gives the pin connected to the positive channel
static const uint8_t adc_pins[] = {
@ -137,6 +136,7 @@ static const uint8_t adc_pins[] = {
ADC_TEMPERATURE_PIN, // [16] vtemp
0, // [17] vbat/3
0, // [18] vref
0,
0, // [0] vssa ADC 2
GPIO('A', 0), // [1]
GPIO('A', 1), // [2]