125 lines
10 KiB
C
125 lines
10 KiB
C
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2012, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following condition is met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#ifndef _SAM3XA_PIOB_INSTANCE_
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#define _SAM3XA_PIOB_INSTANCE_
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/* ========== Register definition for PIOB peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
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#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
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#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
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#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
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#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
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#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */
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#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
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#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
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#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
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#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
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#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
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#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
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#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
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#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
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#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
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#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
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#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
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#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
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#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
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#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
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#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
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#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
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#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
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#define REG_PIOB_ABSR (0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
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#define REG_PIOB_SCIFSR (0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
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#define REG_PIOB_DIFSR (0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
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#define REG_PIOB_IFDGSR (0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
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#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
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#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
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#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
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#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
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#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
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#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
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#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
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#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
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#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
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#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
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#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
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#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
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#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
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#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */
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#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
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#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
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#else
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#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
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#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
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#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
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#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
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#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
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#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
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#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
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#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
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#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
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#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
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#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
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#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
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#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
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#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
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#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
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#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
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#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
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#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
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#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
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#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
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#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
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#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
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#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
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#define REG_PIOB_ABSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
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#define REG_PIOB_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
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#define REG_PIOB_DIFSR (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
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#define REG_PIOB_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
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#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
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#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
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#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
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#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
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#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
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#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
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#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
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#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
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#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
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#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
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#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
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#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
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#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
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#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
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#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
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#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3XA_PIOB_INSTANCE_ */
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