2019-07-29 06:15:54 +03:00
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// STM32 serial
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2019-07-24 06:51:31 +03:00
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_SERIAL_BAUD
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2019-08-21 20:52:43 +03:00
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#include "board/armcm_boot.h" // armcm_enable_irq
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2019-07-24 06:51:31 +03:00
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#include "board/serial_irq.h" // serial_rx_byte
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#include "sched.h" // DECL_INIT
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2019-07-29 05:27:32 +03:00
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// Select the configured serial port
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2021-03-18 20:20:54 +03:00
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#if CONFIG_STM32_SERIAL_USART1
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2020-01-23 19:33:11 +03:00
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA10,PA9");
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#define GPIO_Rx GPIO('A', 10)
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#define GPIO_Tx GPIO('A', 9)
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#define USARTx USART1
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#define USARTx_IRQn USART1_IRQn
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2021-05-25 04:17:51 +03:00
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#elif CONFIG_STM32_SERIAL_USART1_ALT_PB7_PB6
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB7,PB6");
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#define GPIO_Rx GPIO('B', 7)
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#define GPIO_Tx GPIO('B', 6)
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#define USARTx USART1
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#define USARTx_IRQn USART1_IRQn
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2021-03-18 20:20:54 +03:00
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#elif CONFIG_STM32_SERIAL_USART2
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2020-01-23 19:33:11 +03:00
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2");
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#define GPIO_Rx GPIO('A', 3)
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#define GPIO_Tx GPIO('A', 2)
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#define USARTx USART2
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#define USARTx_IRQn USART2_IRQn
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2021-05-25 04:17:51 +03:00
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#elif CONFIG_STM32_SERIAL_USART2_ALT_PD6_PD5
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD6,PD5");
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#define GPIO_Rx GPIO('D', 6)
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#define GPIO_Tx GPIO('D', 5)
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#define USARTx USART2
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#define USARTx_IRQn USART2_IRQn
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2021-03-18 20:20:54 +03:00
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#elif CONFIG_STM32_SERIAL_USART3
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB11,PB10");
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#define GPIO_Rx GPIO('B', 11)
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#define GPIO_Tx GPIO('B', 10)
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#define USARTx USART3
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#define USARTx_IRQn USART3_IRQn
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2021-05-25 04:06:04 +03:00
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#elif CONFIG_STM32_SERIAL_USART3_ALT_PD9_PD8
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2021-03-18 20:20:54 +03:00
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD9,PD8");
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#define GPIO_Rx GPIO('D', 9)
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#define GPIO_Tx GPIO('D', 8)
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2020-01-23 19:33:11 +03:00
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#define USARTx USART3
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#define USARTx_IRQn USART3_IRQn
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2019-07-29 05:27:32 +03:00
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#endif
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2019-07-24 06:51:31 +03:00
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#define CR1_FLAGS (USART_CR1_UE | USART_CR1_RE | USART_CR1_TE \
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| USART_CR1_RXNEIE)
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2019-08-21 20:52:43 +03:00
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void
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2019-07-29 05:27:32 +03:00
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USARTx_IRQHandler(void)
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2019-07-24 06:51:31 +03:00
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{
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2019-07-29 05:27:32 +03:00
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uint32_t sr = USARTx->SR;
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2022-10-31 20:03:11 +03:00
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if (sr & (USART_SR_RXNE | USART_SR_ORE)) {
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// The ORE flag is automatically cleared by reading SR, followed
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// by reading DR.
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2019-07-29 05:27:32 +03:00
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serial_rx_byte(USARTx->DR);
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}
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2019-07-29 05:27:32 +03:00
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if (sr & USART_SR_TXE && USARTx->CR1 & USART_CR1_TXEIE) {
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2019-07-24 06:51:31 +03:00
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uint8_t data;
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int ret = serial_get_tx_byte(&data);
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if (ret)
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2019-07-29 05:27:32 +03:00
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USARTx->CR1 = CR1_FLAGS;
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2019-07-24 06:51:31 +03:00
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else
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USARTx->DR = data;
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2019-07-24 06:51:31 +03:00
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}
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}
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void
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serial_enable_tx_irq(void)
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{
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2019-07-29 05:27:32 +03:00
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USARTx->CR1 = CR1_FLAGS | USART_CR1_TXEIE;
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2019-07-24 06:51:31 +03:00
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}
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2019-08-22 15:48:10 +03:00
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void
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serial_init(void)
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{
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enable_pclock((uint32_t)USARTx);
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uint32_t pclk = get_pclock_frequency((uint32_t)USARTx);
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uint32_t div = DIV_ROUND_CLOSEST(pclk, CONFIG_SERIAL_BAUD);
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USARTx->BRR = (((div / 16) << USART_BRR_DIV_Mantissa_Pos)
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| ((div % 16) << USART_BRR_DIV_Fraction_Pos));
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USARTx->CR1 = CR1_FLAGS;
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2019-08-21 20:52:43 +03:00
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armcm_enable_irq(USARTx_IRQHandler, USARTx_IRQn, 0);
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2019-08-22 15:48:10 +03:00
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gpio_peripheral(GPIO_Rx, GPIO_FUNCTION(7), 1);
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gpio_peripheral(GPIO_Tx, GPIO_FUNCTION(7), 0);
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}
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DECL_INIT(serial_init);
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