2019-01-15 00:26:47 +03:00
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/**
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* \file
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*
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* \brief Instance description for RTC
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*
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2022-09-29 19:17:20 +03:00
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* Copyright (c) 2019 Microchip Technology Inc.
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2019-01-15 00:26:47 +03:00
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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2022-09-29 19:17:20 +03:00
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#ifndef _SAME54_RTC_INSTANCE_
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#define _SAME54_RTC_INSTANCE_
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2019-01-15 00:26:47 +03:00
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/* ========== Register definition for RTC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */
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#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */
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#define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */
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#define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */
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#define REG_RTC_GP2 (0x40002448) /**< \brief (RTC) General Purpose 2 */
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#define REG_RTC_GP3 (0x4000244C) /**< \brief (RTC) General Purpose 3 */
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#define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */
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#define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */
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#define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */
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#define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */
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#define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */
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#define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */
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#define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */
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#define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */
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#define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */
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#define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */
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#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */
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#define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */
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#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */
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#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
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#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
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#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
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#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
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#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
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#define REG_RTC_MODE0_COMP1 (0x40002424) /**< \brief (RTC) MODE0 Compare 1 Value */
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#define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */
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#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */
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#define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */
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#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */
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#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
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#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
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#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
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#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
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#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
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#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
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#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
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#define REG_RTC_MODE1_COMP2 (0x40002424) /**< \brief (RTC) MODE1 Compare 2 Value */
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#define REG_RTC_MODE1_COMP3 (0x40002426) /**< \brief (RTC) MODE1 Compare 3 Value */
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#define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */
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#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */
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#define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */
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#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */
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#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
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#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
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#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
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#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
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#define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */
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#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
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#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
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#define REG_RTC_MODE2_ALARM_ALARM1 (0x40002428) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
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#define REG_RTC_MODE2_ALARM_MASK1 (0x4000242C) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
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#else
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#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
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#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
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#define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */
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#define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */
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#define REG_RTC_GP2 (*(RwReg *)0x40002448UL) /**< \brief (RTC) General Purpose 2 */
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#define REG_RTC_GP3 (*(RwReg *)0x4000244CUL) /**< \brief (RTC) General Purpose 3 */
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#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */
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#define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */
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#define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */
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#define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */
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#define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */
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#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */
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#define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */
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#define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */
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#define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */
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#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */
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#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
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#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */
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#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
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#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
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#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
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#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
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#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
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#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
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#define REG_RTC_MODE0_COMP1 (*(RwReg *)0x40002424UL) /**< \brief (RTC) MODE0 Compare 1 Value */
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#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */
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#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
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#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */
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#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
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#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
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#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
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#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
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#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
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#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
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#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
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#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
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#define REG_RTC_MODE1_COMP2 (*(RwReg16*)0x40002424UL) /**< \brief (RTC) MODE1 Compare 2 Value */
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#define REG_RTC_MODE1_COMP3 (*(RwReg16*)0x40002426UL) /**< \brief (RTC) MODE1 Compare 3 Value */
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#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */
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#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
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#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */
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#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
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#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
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#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
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#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
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#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
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#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */
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#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
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#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
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#define REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg *)0x40002428UL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
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#define REG_RTC_MODE2_ALARM_MASK1 (*(RwReg8 *)0x4000242CUL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for RTC peripheral ========== */
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#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger
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#define RTC_GPR_NUM 4 // Number of General-Purpose Registers
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#define RTC_NUM_OF_ALARMS 2 // Number of Alarms
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#define RTC_NUM_OF_BKREGS 8 // Number of Backup Registers
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#define RTC_NUM_OF_COMP16 4 // Number of 16-bit Comparators
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#define RTC_NUM_OF_COMP32 2 // Number of 32-bit Comparators
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#define RTC_NUM_OF_TAMPERS 5 // Number of Tamper Inputs
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#define RTC_PER_NUM 8 // Number of Periodic Intervals
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2022-09-29 19:17:20 +03:00
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#endif /* _SAME54_RTC_INSTANCE_ */
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