74 lines
2.5 KiB
C
74 lines
2.5 KiB
C
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// Code to setup peripheral clocks on the SAMD21
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//
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// Copyright (C) 2018 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_FREQ
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#include "compiler.h" // DIV_ROUND_CLOSEST
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#include "internal.h" // enable_pclock
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#include "samd21.h" // GCLK
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void
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enable_pclock(uint32_t clock_id, uint32_t pmask)
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{
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(clock_id) | GCLK_CLKCTRL_GEN_GCLK0
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| GCLK_CLKCTRL_CLKEN);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
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;
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PM->APBCMASK.reg |= pmask;
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}
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#define CLK_MAIN 0
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#define CLK_32K 1
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#define MCLK_DFLL48M 0
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#define CLK_32K_FREQ 32768
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void
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SystemInit(void)
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{
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// Setup flash to work with 48Mhz clock
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS_HALF;
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// Enable external 32Khz crystal
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uint32_t val = (SYSCTRL_XOSC32K_STARTUP(6)
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| SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K);
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SYSCTRL->XOSC32K.reg = val;
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SYSCTRL->XOSC32K.reg = val | SYSCTRL_XOSC32K_ENABLE;
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while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY))
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;
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// Reset GCLK
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GCLK->CTRL.reg = GCLK_CTRL_SWRST;
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while (GCLK->CTRL.reg & GCLK_CTRL_SWRST)
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;
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// Route 32Khz clock to DFLL48M
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLK_32K);
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLK_32K)
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| GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_GENEN);
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_ID(MCLK_DFLL48M)
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| GCLK_CLKCTRL_GEN(CLK_32K) | GCLK_CLKCTRL_CLKEN);
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// Configure DFLL48M clock
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SYSCTRL->DFLLCTRL.reg = 0;
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uint32_t mul = DIV_ROUND_CLOSEST(CONFIG_CLOCK_FREQ, CLK_32K_FREQ);
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SYSCTRL->DFLLMUL.reg = (SYSCTRL_DFLLMUL_CSTEP(31)
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| SYSCTRL_DFLLMUL_FSTEP(511)
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| SYSCTRL_DFLLMUL_MUL(mul));
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SYSCTRL->DFLLCTRL.reg = (SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK
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| SYSCTRL_DFLLCTRL_QLDIS
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| SYSCTRL_DFLLCTRL_ENABLE);
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uint32_t ready = (SYSCTRL_PCLKSR_DFLLRDY | SYSCTRL_PCLKSR_DFLLLCKC
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| SYSCTRL_PCLKSR_DFLLLCKF);
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while ((SYSCTRL->PCLKSR.reg & ready) != ready)
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;
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// Switch main clock to DFLL48M clock
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(CLK_MAIN);
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(CLK_MAIN)
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| GCLK_GENCTRL_SRC_DFLL48M
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| GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN);
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}
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